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ATWILC1000B-MUT Datasheet(PDF) 25 Page - ATMEL Corporation |
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ATWILC1000B-MUT Datasheet(HTML) 25 Page - ATMEL Corporation |
25 / 38 page ATWILC1000B-MUT [DATASHEET] Atmel-42491B-ATWILC1000B-MUT_Datasheet_03/2016 2 5 25 Table 8-7. SPI Master Interface Pin Mapping Pin # Pin Name SPI Function 28 GPIO3 SCK: Serial Clock Output 29 GPIO4 SCK: Active Low Slave Select Output 30 GPIO5 TXD: Serial Data Transmit Output (MOSI) 31 GPIO6 RXD: Serial Data Receive Input (MISO) The SPI Master timing is provided in Figure 8-4 and Table 8-8. Figure 8-4. SPI Master Timing Diagram fSCK tWH tLH tHL tWL tODLY tISU tIHD SCK SSN, TXD RXD Table 8-8. SPI Master Timing Parameters Parameter Symbol Min. Max. Units Clock Output Frequency fSCK 48 MHz Clock Low Pulse Width tWL 5 ns Clock High Pulse Width tWH 5 Clock Rise Time tLH 5 Clock Fall Time tHL 5 Input Setup Time tISU 5 Input Hold Time tIHD 5 Output Delay tODLY 0 5 8.5 SDIO Slave Interface The ATWILC1000B SDIO Slave is a full speed interface. The interface supports the 1-bit/4-bit SD transfer mode at the clock range of 0-50MHz. The Host can use this interface to read and write from any register within the chip as well as configure the ATWILC1000B for data DMA. To use this interface, pin 9 (SDIO_SPI_CFG) must be grounded. The SDIO Slave pins are mapped as shown in Table 8-9. |
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