FLASH

AS8F512K32

Austin Semiconductor, Inc.

AS8F512K32

Rev. 4.0 6/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

Chip Erase Command

Chip-erase is a six-bus-cycle command sequence. The first

three bus cycles put the device into the erase-setup state. The

next two bus cycles unlock the erase mode. The sixth bus cycle

loads the chip erase command. This command sequence is

required to ensure that the memory contents are not erased

accidentally. The rising edge of WE\ starts the chip erase op-

eration. Any further commands written to the device during

the chip erase operation is ignored.

The embedded chip erase function automatically provides

voltage and timings needed to program and verify all the memory

cells prior to electrical erase. It then erases and verifies the cell

margin automatically. The user is not required to program the

memory cells prior to erase. The status of the device during the

automatic chip erase operation can be monitored for comple-

tion using the data-polling feature. See the "operation status"

section for a full description.

Sector-Erase Command

Sector erase is a six-bus-cycle command sequence. The

first three bus cycles put the device into the erase-setup state.

The next two bus cycles unlock the erase mode. The sixth bus

cycle loads the sector erase command and the sector address

location to be erased. Any address location within the desired

sector can be used. The addresses are latched on the falling

edge of WE\ in the sixth bus cycle. After a delay of 100-ms

from the rising edge of WE\, the sector erase operation begins

in the selected source.

Sectors can be selected to be erased concurrently during

the sector-erase command sequence. For each additional sec-

tor selected for erase, another bus cycle is issued. The bus

cycle loads the next sector-address location and the sector-

erase command. The time between the end of the previous bus

cycle and the start of the next bus cycle must be less than 100

ms-other wise, the new sector location is not loaded. A time

delay of 100 ms from the raising edge of the last WE\ starts the

sector erase operation. If there is a falling edge of WE\ within

the 100 ms time delay, the timer is reset.

One to eight sector address locations can be loaded in any

order. The state of the delay timer can be monitored using the

sector-erase-delay indicator (DQ3). If DQ3 is logic low, the time

delay has not expired. See the “operation status” for the full

description.

Any commands other than erase-suspend (B0) or sector

erase (30) written to the device during the sector erase opera-

tion causes the device to exit the sector erase mode. The con-

tents of the sector(s) selected for erase is not valid. To com-

plete the sector-erase operation, reissue the sector erase com-

mand.

The embedded sector erase function automatically

provides voltage and timings needed to program and verify all

the memory cells prior to electrical erase and then erases and

verifies the cell margin automatically. The user is not required

to program the memory cells prior to erase. The status of the

device during the automatic sector erase operation can be moni-

tored for completion using the data-polling feature or the toggle

bit feature. See the "operation status" section for a full de-

scription.

Erase-Suspend Command

Sector-erase operations may be interrupted by the erase-

suspend command (B0) , in order to read data from an unaltered

sectors of the device. Erase-suspend is a one-bus-cycle com-

mand. The addresses can be V

IL

or V

IH

and the erase-suspend

command (B0) is latched on the rising edge of WE\. Once the

sector-erase operation is in progress, the erase-suspend com-

mand request the internal write-state-machine to halt operation

at predetermined break points. The erase-suspend command is

valid only during the sector-erase operation and is valid only

during the byte-programming and chip-erase operations. The

sector-erase delay timer expires immediately if the erase-sus-

pend command is issued while the delay is active.

After erase-suspend is issued, the device takes between

0.1ms and 15 ms to suspend the operation. The toggle bit must

be monitored to determine when the suspend has been ex-

ecuted. When the toggle bit stops toggling, data can be read

from sectors that are not selected for erase. See the “operation

status” section for a full definition. Reading from a sector

marked for erase can result in invalid data.

Once the sector-erase operation is suspended, further

writes of the erase-suspend command are ignored. Any com-

mand other than erase-suspend (B0) or erase-resume (30H)

written to the device during the erase-suspend mode causes

the device to exit the suspend mode. To complete the sector-

erase operation, reissue the sector-erase command sequence.

Erase-Resume Command

The erase-resume command (30H) restarts a suspended

sector erase operation from where it was halted to completion.

Erase-resume is a one-bus-cycle command. The addresses can

be V

IL

or V

IH

and the erase-resume command (30H) is latched

on the rising edge of WE\. When an erase-suspend/ erase-

resume command combination is written, the internal pulse

counter (exceed timing limit) is reset. The erase-resume com-

mand is valid only in the erase-suspend state. After the erase-

resume command is executed, the device returns to the valid

sector-erase state and further writes of the erase-resume com-

mands are ignored. After the device has resumed the sector-

erase operation, another erase-resume command can be issued

to the device.