DAC100

ASD0011162 Rev. F | Page 3 of 5

4.0

TABLE I

Parameter

Symbol

Conditions 1/

Sub-

group

Limit

Min

Limit

Max

Units

Power supply current

I+

1, 2, 3

8.33

mA

I-

1, 2, 3

8.33

Full range output voltage

to V-

1, 2, 3

10.0

11.1

V

Zero scale output voltage

1, 2, 3

±.013

%FS

Integral nonlinearity

NL

± ½ LSB – 9 Bits

1, 2, 3

±0.1

Full scale temperature

coefficient

pin tied to V-

8

±60

ppm/°

C

Logic inputs high

Measured with respect to output

pin allowing

≤ ±½ LSB change

with

1, 2, 3

2.1

V

Logic inputs low

Measured with respect to output

pin allowing

≤ ±½ LSB change

with

1, 2, 3

0.7

Logic input current high

1, 2, 3

5

µA

Logic input current low

1, 2, 3

5

Power supply sensitivity

PSS

±6V to ±18V

1, 2, 3

±0.1

%/V

Monotonicity 2/

Measured at each major carry

code point

1

0

µA

Settling time 3/

9

375

nS

Table I notes:

2/ The change in output current either increases or remains the same for an increasing digital input

code.

Input pulse characteristics:

Input frequency = 1MHz square wave, 50% duty cycle.

Input amplitude = 0V to 2.1V

Input signal =

Measurement referenced to input High-to-Low Transition. DUT Settling Time to ±0.05 % FS