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SLG46400 Datasheet(PDF) 70 Page - Dialog Semiconductor |
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SLG46400 Datasheet(HTML) 70 Page - Dialog Semiconductor |
70 / 95 page 000-0046400-109 Page 64 of 89 SLG46400 19.2 DFF/LATCH Selection Each of the four DFF/LATCH logic cells have a selection bit that is used to define if the logic cell will be used as a D Flip-Flop or a Latch within the design. Those control bits are shown in the table below. 19.3 DFF/LATCH Register Settings Table 41. DFF/LATCH Register Settings Signal Function Register Bit Address Register Definition DFF/LATCH0 Selection <530> 0: DFF 1: Latch DFF0 Reset or Set Select <531> 0: Reset from Connection Matrix 1 1: Set from Connection Matrix 1 DFF/LATCH1 Selection <532> 0: DFF 1: Latch DFF1 Reset or Set Select <533> 0: Reset from Connection Matrix 18 1: Set from Connection Matrix 18 DFF/LATCH2 Selection <534> 0: DFF 1: Latch DFF/LATCH3 Selection <535> 0: DFF 1: Latch |
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