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SLG46400 Datasheet(PDF) 29 Page - Dialog Semiconductor |
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SLG46400 Datasheet(HTML) 29 Page - Dialog Semiconductor |
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29 / 95 page  000-0046400-109 Page 23 of 89 SLG46400 9.6 ADC Reference Voltage The ADC’s reference voltage (VREF) is controlled by ADC_Vref_sel (reg <720:719>) and the ADC_DAC_Vref (reg <713>). See the Table 12 for reference. For optimal ADC performance, the Ext_Vref value should not be greater than 1.0V. The three reference voltage inputs are chosen from the following: • Bandgap voltage (VBG) of 1V or 0.778V from Internal Source • 1x or 2x External User Defined Voltage Source (PIN 11) • Power Divider of (0.25 or 0.5) * VDD 9.7 ADC Power Down Select Mode The ADC’s power down source is selected by reg <815:814> (shared with the PWM and OSC). When reg <815:814> = ‘01’, the ADC power down is controlled by reg <813>, where if reg <813> = ‘0’, ADC is powered down, and if reg <813> = ‘1’, ADC operates normally. Otherwise the ADC power down is controlled by the connection matrix output 3 signal where a value of “1” will drive the ADC and the PGA to power down mode. The SLG46400 also has a slow/fast power on mode feature controlled by reg<715>. When reg<715> = 0, the ADC is in slow power on mode and the entire analog block is controlled by connection matrix output 3. When reg<715> = 1, ADC is in fast power on mode, where only the ADC will be controlled by connection matrix output 3 and the analog block will remain on. With this feature, the first ADC power on (with the rest of the analog block) will be approximately 20 μs; the next power cycle the ADC power on (ADC only) time is <1ns. 9.8 ADC Clock Source The ADC clock source comes from either the internal RC Oscillator (CLK4ADC/64) or an external clock from PIN 5. The selection is made from the ADC_clk_sel signal via reg <737> where: • The RC Oscillator is used when the ADC_clk_sel is “0” • An external clock from PIN 5 is used when the ADC_clk_sel is “1” The ADC requires 16 clock cycles to sample the analog voltage and output the sampled data. When the internal RC Oscillator is used for providing timing to the ADC, a total of 1024 clock cycles are needed since the CLK4ADC signal is also divided by 64. Figure 5. ADC Reference Voltage Bandgap (1V or 0.778V) 1x or 2x Ext. Vref (PIN 11) VDD *(0.25 or 0.5) 10 00 01 reg <720:719> VREF Table 12. ADC Reference Voltage. reg <720:719> VREF reg <713> = 0 reg <713> = 1 00 VBG (1V) VBG (0.778V) 01 2x Ext_Vref (PIN 11) 1x Ext_Vref (PIN 11) 10 Power Divider (0.5 * VDD) Power Divider (0.25 * VDD) 11 N/A N/A Figure 6. ADC Clock Source 1 0 EXT. CLK (PIN 5) CLK4ADC/64 reg <737> CLK |
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