SLG46533 datasheet(73/185 Pages) DIALOG

Part #	SLG46533

Description	GreenPAK Programmable Mixed-signal Matrix

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Manufacturer	DIALOG [Dialog Semiconductor]

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SLG46533_DS_114

Page 72 of 184

SLG46533

9.4 3-Bit LUT or Pipe Delay Macrocell

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.

When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single

output, which goes back into the connection matrix.

When used as a pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (nRST). The pipe

delay cell is built from 16 D Flip-Flop logic cells that provide the three output options, two of which are user selectable. The DFF

cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The first delay option is fixed at the output

of the first flip-flop stage. The other two outputs (OUT0 and OUT1) provide user selectable options for 1 – 16 stages of delay

There are delay output points for each set of the OUT0 and OUT1 outputs to a 16-input mux that is controlled by reg <1259:1256>

for OUT0 and reg <1263:1260> for OUT1. The 16-input mux is used to select the amount of delay.

The overall time of the delay is based on the clock used in the SLG46533 design. Each DFF cell has a time delay of the inverse

of the clock time (either external clock or the RC Oscillator within the SLG46533). The sum of the number of DFF cells used will

be the total time delay of the Pipe Delay logic cell.

Note: CLK is rising edge triggered.

Figure 28. 3-bit LUT10 or Pipe Delay

3-bit LUT10 OUT

IN1

IN0

From Connection

Matrix Output <98>

From Connection

Matrix Output <99>

IN2

From Connection

Matrix Output <100>

16 Flip-Flops

nRST

IN

CLK

From Connection

Matrix Output <98>

From Connection

Matrix Output <99>

From Connection

Matrix Output <100>

reg <1263:1260>

reg <1259:1256>

To Connection

Matrix Input<26>

To Connection

Matrix Input <25>

OUT1

OUT0

reg <1271>

To Connection

Matrix Input <24>

1 Pipe OUT

S0

S1

S0

S1

LUT Truth

Table

reg <1263:1256>

reg <1270>

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