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X40421S14-C Datasheet(PDF) 6 Page - Xicor Inc.

Part # X40421S14-C
Description  Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch
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Manufacturer  XICOR [Xicor Inc.]
Direct Link  http://www.xicor.com
Logo XICOR - Xicor Inc.

X40421S14-C Datasheet(HTML) 6 Page - Xicor Inc.

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X40420/X40421 – Preliminary
Characteristics subject to change without notice.
6 of 25
REV 1.2.14 7/12/02
www.xicor.com
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming voltage
(Vp) to the WDO pin before a START condition is set up
on SDA. Next, issue on the SDA pin the Slave Address
A0h followed by the Byte Address 03h for VTRIP1 and
0Bh for VTRIP2, followed by 00h for the Data Byte in order
to reset VTRIPx. The STOP bit following a valid write oper-
ation initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation.
After being reset, the value of VTRIPx becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the memory array.
System Battery Switch
As long as VCC exceeds the low voltage detect threshold
VTRIP, VOUT is connected to VCC through a 5 Ohm (typi-
cal) switch. When the VCC has fallen below V1TRIP, then
VCC is applied to VOUT if VCC is or equal to or greater
than VBATT – 0.03V. When VCC drops to less than VBATT
– 0.03V, then VOUT is connected to VBATT through an 80
Ohm (typical) switch. VOUT typically supplies the system
static RAM voltage, so the switchover circuit operates to
protect the contents of the static RAM during a power fail-
ure. Typically, when VCC has failed, the SRAMs go into a
lower power state and draw much less current than in
their active mode. When VCC returns, VOUT switches
back to VCC when VCC exceeds VBATT + 0.03V. There is
a 60mV hysteresis around this battery switch threshold to
prevent oscillations between supplies.
While VCC is connected to VOUT the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Operation
The device is in normal operation with VCC as long as
VCC > VTRIP1. It switches to the battery backup mode
when VCC goes away.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, and BP. The X40420 will not
acknowledge any data bytes written after the first byte is
entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Condition
Mode of Operation
VCC > VTRIP1
Normal Operation
VCC > VTRIP1 &
VBATT = 0
Normal Operation without battery
backup capability
0
≤ VCC ≤ VTRIP1
and VCC < VBATT
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
7
6
543
21
0
PUP1 WD1
WD0
BP
0
RWEL WEL PUP0
Figure 5. Sample VTRIP Reset Circuit
1
6
2
7
14
13
9
8
X40420
VTRIP1
Adj.
VP
RESET
4.7K
SDA
SCL
µC
Adjust
Run
V2FAIL
VTRIP2
Adj.


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