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PC755CMGSU300LE Datasheet(PDF) 5 Page - ATMEL Corporation |
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PC755CMGSU300LE Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 50 page 5 PC755/745 2138D–HIREL–06/03 – Supports flow through (register-buffer) synchronous burst SRAMs, pipelined (register-register) synchronous burst SRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late-write synchronous burst SRAMs – L2 configurable to direct mapped SRAM interface or split cache/direct mapped or private memory – Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported – 64-bit data bus – Selectable interface voltages of 2.5V and 3.3V – Parity checking on both L2 address and data • Memory Management Unit – 128 entry, 2-way set associative instruction TLB – 128 entry, 2-way set associative data TLB – Hardware reload for TLBs – Hardware or optional software tablewalk support – 8 instruction BATs and 8 data BATs – 8 SPRGs, for assistance with software tablewalks – Virtual memory support for up to 4 hexabytes (2 52) of virtual memory – Real memory support for up to 4 gigabytes (2 32) of physical memory • Bus Interface – Compatible with 60X processor interface – 32-bit address bus – 64-bit data bus, 32-bit mode selectable – Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x supported – Selectable interface voltages of 2.5V and 3.3V. – Parity checking on both address and data busses • Power Management – Low-power design with thermal requirements very similar to PC740/750. – Selectable interface voltage of 1.8V/2.0V can reduce power in output buffers (compared to 3.3V) – Three static power saving modes: doze, nap, and sleep – Dynamic power management • Testability – LSSD scan design – IEEE 1149.1 JTAG interface • Integrated Thermal Management Assist Unit – One-ship thermal sensor and control logic – Thermal Management Interrupt for software regulation of junction temperature |
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