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PC755CVGU366LE Datasheet(PDF) 3 Page - ATMEL Corporation |
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PC755CVGU366LE Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 50 page  3 PC755/745 2138D–HIREL–06/03 General Parameters The following list provides a summary of the general parameters of the PC755: Features This section summarizes features of the PC755’s implementation of the PowerPC archi- tecture. Major features of the PC755 are as follows: • Branch Processing Unit – Four instructions fetched per clock – One branch processed per cycle (plus resolving 2 speculations) – Up to 1 speculative stream in execution, 1 additional speculative stream in fetch – 512-entry branch history table (BHT) for dynamic prediction – 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch delay slots • Dispatch Unit – Full hardware detection of dependencies (resolved in the execution units) – Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point) – Serialization control (predispatch, postdispatch, execution serialization) • Decode – Register file access – Forwarding control – Partial instruction decode • Completion – 6 entry completion buffer – Instruction tracking and peak completion of two instructions per cycle – Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization and all instruction flow changes • Fixed Point Units (FXUs) that share 32 GPRs for Integer Operands – Fixed Point Unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical – Fixed Point Unit 2 (FXU2)-shift, rotate, arithmetic, logical Technology 0.22 µm CMOS, six-layer metal Die size 6.61 mm x 7.73 mm (51 mm 2) Transistor count 6.75 million Logic design Fully-static Packages PC745 Surface mount 255 Plastic Ball Grid Array (PBGA) PC755 Surface mount 360 Plastic Ball Grid Array (PBGA) Surface mount 360 Ceramic Ball Grid Array (CI-CGA, CBGA, HiTCE) Core power supply 2V ± 100 mV DC (nominal; some parts support core voltages down to 1.8V; see Table 5 for recommended operating conditions) I/O power supply 2.5V ± 100 mV DC or 3.3V ± 165 mV DC (input thresholds are configuration pin selectable) |
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