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AD5415 Datasheet(HTML) 5 Page - Analog Devices

Part No. AD5415
Description  Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5415 Datasheet(HTML) 5 Page - Analog Devices

 
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AD5415
Rev. 0 | Page 5 of 28
TIMING CHARACTERISTICS
Temperature range for Y Version: −40°C to +125°C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments1
fSCLK
50
MHz max
Maximum clock frequency
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
4
ns min
Data hold time
t7
5
ns min
SYNC rising edge to SCLK falling edge
t8
30
ns min
Minimum SYNC high time
t9
0
ns min
SCLK falling edge to LDAC falling edge
t10
12
ns min
LDAC pulse width
t11
10
ns min
SCLK falling edge to LDAC rising edge
t122
25
ns min
SCLK active edge to SDO valid, strong SDO driver
60
ns min
SCLK active edge to SDO valid, weak SDO driver
1 Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in
.
Figure 4
t1
t2
t3
t7
t8
t4
t5
t6
t9
t10
t11
DB15
DB0
SCLK
DIN
LDAC1
LDAC2
SYNC
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram


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