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AD5415 Datasheet(HTML) 6 Page - Analog Devices

Part No. AD5415
Description  Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5415 Datasheet(HTML) 6 Page - Analog Devices

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AD5415
Rev. 0 | Page 6 of 28
t8
t7
t12
t1
t3
t2
t4
t5
t6
DB15
(N)
DB15
(N+1)
DB0
(N)
DB0
(N+1)
DB15
(N)
DB0
(N)
SCLK
SYNC
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200
µAI
OL
200
µAI
OH
TO OUTPUT
PIN
CL
50pF
VOH (MIN) + VOL (MAX)
2
Figure 4. Load Circuit for SDO Timing Specifications


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