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AD5255BRU25-RL7 Datasheet(HTML) 5 Page - Analog Devices

Part No. AD5255BRU25-RL7
Description  3-Channel Digital Potentiometer with Nonvolatile Memory
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5255BRU25-RL7 Datasheet(HTML) 5 Page - Analog Devices

 
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AD5255
Rev. 0 | Page 5 of 20
ELECTRICAL CHARACTERISTICS
Single Supply: VDD = 3 V to 5.5 V and −40°C < TA< +85°C, unless otherwise noted.
Dual Supply: VDD = +2.25 V or +2.75 V , VSS = −2.25 V or −2.75 V and −40°C < TA < + 85°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS5, 7
Bandwidth −3 dB
BW
VDD/VSS = ±2.5 V, RAB = 25 kΩ/250 kΩ
125/12
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.05
%
VW Settling Time
tS
VA = VDD, VB = 0 V,
VW = 0.50% error band,
code 0x000 to 0x100, RAB = 25 kΩ/250 kΩ
4/36
µs
Resistor Noise Spectral Density
eN_WB
RAB = 25 kΩ/250 kΩ, TA = 25°C
14/45
nV√Hz
Digital Crosstalk
CT
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
−80
dB
Analog Crosstalk
CAT
Signal input at A0 and measure output
at W1, f = 1 kHz
−72
dB
INTERFACE TIMING CHARACTERISTICS
(apply to all parts) (Notes8, 9)
SCL Clock Frequency
fSCL
400
kHz
tBUF Bus Free Time between Stop and
Start
t1
1.3
µs
tHD;STA Hold Time (Repeated Start)
t2
After this period the first clock pulse is
generated
600
ns
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
50
µs
tSU;STA Setup Time for Start Condition
t5
600
ns
tHD;DAT Data Hold Time
t6
900
ns
tSU;DAT Data Setup Time
t7
100
ns
tR Rise Time of Both SDA and SCL
Signals
t8
300
ns
tF Fall Time of Both SDA and SCL
Signals
t9
300
ns
tSU;STO Setup Time for Stop Condition
t10
600
ns
EEMEM Data Storing Time
tEEMEM_STORE
26
ms
EEMEM Data Restoring Time at
Power-On
tEEMEM_RESTORE1
360
µs
EEMEM Data Restoring Time on
Restore
tEEMEM_RESTORE2
360
µs
Command or Reset Operation
EEMEM Data Rewritable Time
tEEMEM_REWRITE
540
µs
FLASH/EE MEMORY RELIABILITY
Endurance10
100
kcycles
Data Retention11
55°C
100
years
1 Typical represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
7 All dynamic characteristics use VDD = 5 V.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 See the timing diagram for location of measured values.
10 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at −40°C, +25°C, and +85°C, typical endurance at 25°C is 700,000 cycles.
11 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
derates with junction temperature.


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