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CY7C10211B-10ZC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY7C10211B-10ZC
Description  1-Mbit (64K x 16) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C10211B-10ZC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY7C1021B
CY7C10211B
Document #: 38-05145 Rev. *A
Page 4 of 10
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8pF
COUT
Output Capacitance
8
pF
AC Test Loads and Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R 481
R 481
R2
255
R2
255
167
Equivalent to:
THÉVENIN
EQUIVALENT
1.73V
30 pF
Rise Time: 1 V/ns
Fall Time:1 V/ns
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R 481
R2
255
R2
255
167
Equivalent to:
THÉVENIN
EQUIVALENT
1.73V
30 pF
Rise Time: 1 V/ns
Fall Time:1 V/ns
Switching Characteristics[6] Over the Operating Range
Parameter
Description
7C10211B-10
7C1021B-12
7C1021B-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
10
12
15
ns
tAA
Address to Data Valid
10
12
15
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low Z[7]
00
0
ns
tHZOE
OE HIGH to High Z[7, 8]
56
7
ns
tLZCE
CE LOW to Low Z[7]
33
3
ns
tHZCE
CE HIGH to High Z[7, 8]
56
7
ns
tPU
CE LOW to Power-Up
0
0
0
ns
tPD
CE HIGH to Power-Down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low Z
0
0
0
ns
tHZBE
Byte Disable to High Z
5
6
7
ns
Write Cycle[9]
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tSD
Data Set-Up to Write End
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.


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