 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SPMC802B-PD04 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
|
||||||||||||||||||||||||||||||
SPMC802B-PD04 Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
|
|
11 / 27 page  SPMC802B recover the normal operation from the next address of STOP mode interrupt point with 1024 fTM1 clock cycle recovery time for stable oscillation. To confirm the external interrupt events can wake up the system, the corresponding interrupt enable bits must be set before entering the STOP mode. There are two write paths. One is come from direct write mode through address $0008, another is come from indexed write mode through indexed address $08. The purpose for the dual write paths is for backward compatibility. The option incap is used to inhibit the STOP function coming from the direct write cycle of SNW to improve the system reliability. The indexed write for this register will be described in detail later. 5.10. Reset There are five kinds of reset resource for the system, Power On Reset (POR), External Reset (PB4), Low Voltage Reset (LVR), Watchdog Timer Reset (WDT), and Illegal Address Reset (IAR). These reset sources can be concluded as external events and internal events. The external events are come from the power line, or external trigger event. The internal events are come from the program exceptions or internal software reset event. 5.11. Reset Management Registers There are four registers implemented for reset event management, Stack Limit Register (SLR), System Guard Register (SGR), System Control Register (SCR), and System Stop & Wait Register (SNW). The read of these registers uses direct access. Reading the registers through page 0 addresses can get the contents directly. A specific write cycle, named indexed write cycle, is implemented to have higher reliability of content updates. The indexed addresses for these registers are same as the direct addresses used in read cycle. 5.11.1. Indexed write cycle The procedure of indexed write cycle is formed with two consecutive write cycle of page 0. Only a write with address $003E, called write-index cycle, followed with a write with address $003F, called write-data cycle, can program the reset management registers. The intersections in between these two write cycles are allowed only for the code pre-fetches, means ROM area read cycles. If a ROM-write cycle or an access cycle neither a ROM-read cycle nor a write-data cycle is executed after the write-index cycle, the indexed write cycle will be abnormal terminated without any data updates on these registers. To prevent abnormal termination of the indexed write cycle, programmers should handle the cycle much carefully. The interrupts should be disabled to prevent unpredicted intersections. © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 AUG. 07, 2002 Version: 1.0 |
Similar Part No. - SPMC802B-PD04 |
|
Similar Description - SPMC802B-PD04 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
