TMS626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997

5

POST OFFICE BOX 1443

operation (continued)

COMMAND‡

STATE OF

BANK(S)

DQML

DQMU§

(n)

DATA IN

(n)

DATA OUT

(n + 2)

MNEMONIC

—

T = deac

and

B = deac

X

N/A

Hi-Z

—

—

T = actv

and

B = actv

( no access operation )¶

X

N/A

Hi-Z

—

Data-in enable

T = write

or

B = write

L

V

N/A

ENBL

Data-in mask

T = write

or

B = write

H

M

N/A

MASK

Data-out enable

T = read

or

B = read

L

N/A

V

ENBL

Data-out mask

T = read

or

B = read

H

N/A

Hi-Z

MASK

† For execution of these commands on cycle n:

– CKE (n) must be high, or

–tCESP must be satisfied for power-down exit, or

–tCESP and tRC must be satisfied for self-refresh exit, or

–tCES and nCLE must be satisfied for clock suspend exit.

CS(n), RAS(n), CAS(n), W(n), and A0 – A11 are don’t cares.

‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.

§ DQML controls D 0 – D 7 and Q 0 – Q 7.

DQMU controls D 8 – D 15 and Q 8 – Q15.

¶ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle

of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write

operation.

Legend:

n

= CLK cycle number

L

= Logic low

H

= Logic high

X

= Don’t care, either logic low or logic high

V

= Valid

M

= Masked input data

N/A

= Not applicable

T

= Bank T

B

= Bank B

actv

= Activated

deac = Deactivated

write = Activated and accepting data inputs on cycle n

read

= Activated and delivering data outputs on cycle (n + 2)