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COP310C Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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COP310C Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 20 page  Functional Description (Continued) The SIO register functions as a 4-bit serial-inserial-out shift register or as a binary counter depending upon the con- tents of the EN register (See EN register description be- low) Its contents can be exchanged with A allowing it to input or output a continuous serial data stream With SIO functioning as a serial-inserial-out shift register and SK as a sync clock the COP410C411C is MICROWIRE com- patible The D register provides four general purpose outputs and is used as the destination register for the 4-bit contents of Bd The XAS instruction copies C into the SKL latch In the counter mode SK is the output of SKL in the shift register mode SK is a sync clock inhibited when SKL is a logic ‘‘0’’ The EN register is an internal 4-bit register loaded under program control by the LEI instruction The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN register (EN3 – EN0) 1 The least significant bit of the enable register EN0 se- lects the SIO register as either a 4-bit shift register or as a 4-bit binary counter With EN0 set SIO is an asynchro- nous binary counter decrementing its value by one upon each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI input Each pulse must be at least two instruction cycles wide SK outputs the value of SKL The SO output is equal to the value of EN3 With EN0 reset SIO is a serial shift register shifting left each instruction cycle time The data present at SI is shifted into the least significant bit of SIO SO can be enabled to output the most significant bit of SIO each instruction cycle time (See 4 below) The SK output becomes a logic-controlled clock 2 EN 1 is not used it has no effect on the COP410C411C 3 With EN2 set the L drivers are enabled to output the data in Q to the L IO ports Resetting EN2 disables the L drivers placing the L IO ports in a high impedance input state 4 EN3 in conjunction with EN0 affects the SO output With EN0 set (binary counter option selected) SO will output the value loaded into EN3 With EN0 reset (serial shift register option selected) setting EN3 enables SO as the output of the SIO shift register outputting serial shifted data each instruction time Resetting EN3 with the serial shift register option selected disables SO as the shift register output data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains reset to ‘‘0’’ INITIALIZATION The internal reset logic will initialize the device upon power- up if the power supply rise time is less than 1 ms and if the operating frequency at CKI is greater than 32 kHz other- wise the external RC network shown in Figure 5 must be connected to the RESET pin The RESET pin is configured as a Schmitt trigger input If not used it should be connect- ed to VCC Initialization will occur whenever a logic ‘‘0’’ is applied to the RESET input providing it stays low for at least three instruction cycle times When VCC power is applied the internal reset logic will keep the chip in initialization mode for up to 2500 instruction cy- cles If the CKI clock is running at a low frequency this could take a long time therefore the internal logic should be disabled by a mask option with initialization controlled solely by RESET pin Note If CKI clock is less than 32 kHz the internal reset logic (Option 25e1) must be disabled and the external RC network must be present Upon initialization the PC register is cleared to 0 (ROM ad- dress 0) and the A B C D EN and G registers are cleared The SK output is enabled as a SYNC output providing a pulse each instruction cycle time Data memory (RAM) is not cleared upon initialization The first instruction at ad- dress 0 must be a CLRA (clear A register) TLDD5015 – 6 RC l 5 c Power Supply Rise Time and RC l 100 c CKI Period FIGURE 5 Power-Up Clear Circuit COP411C If the COP410C is bonded as a 20-pin package it becomes the COP411C illustrated in Figure 2 COP410C411C Con- nection Diagrams Note that the COP411C does not contain D2 D3 G3 or CKO Use of this option of course precludes use of D2 D3 G3 and CKO options All other options are available for the COP411C TABLE I Enable Register Modes Bits EN0 and EN3 EN0 EN3 SIO SI SO SK 0 0 Shift Register Input to Shift 0 If SKL e 1 SK e clock Register If SKL e 0 SK e 0 0 1 Shift Register Input to Shift Serial If SKL e 1 SK e clock Register out If SKL e 0 SK e 0 1 0 Binary Counter Input to Counter 0 SK e SKL 1 1 Binary Counter Input to Counter 1 SK e SKL 8 |
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Similar Description - COP310C |
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