CY7C1541KV18 datasheet(15/27 Pages) CYPRESS

Part #	CY7C1541KV18

Description	72-Mbit QDR짰II SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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15 / 27 page

CY7C1541KV18, CY7C1556KV18

CY7C1543KV18, CY7C1545KV18

Document Number: 001-15700 Rev. *F

Page 15 of 27

TAP Controller Block Diagram

TAP Electrical Characteristics

Over the Operating Range [13, 14, 15]

Parameter

Description

Test Conditions

Min

Max

Unit

VOH1

Output HIGH Voltage

IOH = −2.0 mA

1.4

V

VOH2

Output HIGH Voltage

IOH = −100 μA1.6

V

VOL1

Output LOW Voltage

IOL = 2.0 mA

0.4

V

VOL2

Output LOW Voltage

IOL = 100 μA0.2

V

VIH

Input HIGH Voltage

0.65VDD VDD + 0.3

V

VIL

Input LOW Voltage

–0.3

0.35VDD

V

IX

Input and Output Load Current

GND

≤ V

I ≤ VDD

–5

5

μA

0

1

2

.

29

30

31

Boundary Scan Register

Identification Register

0

1

2

.

108

0

1

2

Instruction Register

Bypass Register

Selection

Circuitry

Selection

Circuitry

TAP Controller

TDI

TDO

TCK

TMS

Notes

13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

14. Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2).

15. All Voltage referenced to Ground.

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