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CY7C1663KV18 Datasheet(PDF) 28 Page - Cypress Semiconductor

Part # CY7C1663KV18
Description  144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1663KV18 Datasheet(HTML) 28 Page - Cypress Semiconductor

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Document Number: 001-44060 Rev. *O
Page 28 of 31
CY7C1663KV18/CY7C1665KV18
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BWS
Byte Write Select
DDR
Double Data Rate
DLL
Delay Lock Loop
FBGA
Fine-Pitch Ball Grid Array
HSTL
High-Speed Transceiver Logic
I/O
Input/Output
JTAG
Joint Test Action Group
LSB
Least Significant Bit
LSBU
Logical Single-Bit Upsets
LMBU
Logical Multi-Bit Upsets
MSB
Most Significant Bit
PLL
Phase Locked Loop
QDR
Quad Data Rate
SEL
Single Event Latch-up
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
Symbol
Unit of Measure
°C
degree Celsius
FIT/Dev
failure in time per device
FIT/Mb
failure in time per mega bit
MHz
megahertz
µA
microampere
µs
microsecond
mA
milliampere
mm
millimeter
ms
millisecond
ns
nanosecond
ohm
pF
picofarad
Vvolt
Wwatt


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