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WED9LC6416V2012BI Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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WED9LC6416V2012BI Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 27 page 6 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED9LC6416V January 2001 Operation Address Used SSCE SSADS SSWE SSOE DQ Deselected Cycle, Power Down None H L X X High-Z WRITE Cycle, Begin Burst External L L L X D READ Cycle, Begin Burst External L L H L Q READ Cycle, Begin Burst External L L H H High-Z READ Cycle, Suspend Burst Current X H H L Q READ Cycle, Suspend Burst Current X H H H High-Z READ Cycle, Suspend Burst Current H H H L Q READ Cycle, Suspend Burst Current H H H H High-Z WRITE Cycle, Suspend Burst Current X H L X D WRITE Cycle, Suspend Burst Current H H L X D NOTE: 1. X means “don’t care”, H means logic HIGH. L means logic LOW. 2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. SSRAM OPERATION TRUTH TABLE SSRAM PARTIAL TRUTH TABLE Function SSWE BWE0 BWE1 BWE2 BWE3 READ H X X X X WRITE one Byte (DQ0-7) L L H H H WRITE all Bytes L L L L L |
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