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74LVC1G175GV Datasheet(PDF) 11 Page - NXP Semiconductors |
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74LVC1G175GV Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 17 page 9397 750 13762 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 01 — 18 October 2004 11 of 17 Philips Semiconductors 74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width and the MR to CP removal time. Test data is given in Table 10. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 8. Load circuitry for switching times. Table 10: Test data Supply voltage Input Load VEXT VCC VI CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 30 pF 1 k Ω open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6 V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6 V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × V CC 001aaa464 MR input CP input Q output tPHL tW trem VM VI GND VI VOH VOL GND VM VM VEXT VCC VI VO mna616 D.U.T. CL RT RL RL PULSE GENERATOR |
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