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AS1704 Datasheet(PDF) 7 Page - ams AG |
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AS1704 Datasheet(HTML) 7 Page - ams AG |
7 / 13 page www.austriamicrosystems.com Revision 1.01 7 - 13 AS1702, AS1703, AS1704, AS1705 austriamicrosystems Data Sheet BTL Amplifier 7.1 BTL Amplifier All devices are designed to drive loads differentially in a bridge-tied load (BTL) configuration. Figure 4. Bridge Tied Load Configuration The BTL configuration doubles the output voltage (illustrated in Figure 4) compared to a single-ended amplifier under similar conditions. Thus, the differential gain of the device (AVD) is twice the closed-loop gain of the input amplifier. The effective gain is given by: Substituting 2 x VOUT(P-P) for VOUT(P-P) into (EQ 3) and (EQ 4) yields four times the output power due to doubling of the output voltage: Since the BTL outputs are biased at mid-supply, there is no net DC voltage across the load. This eliminates the need for the large, expensive, performance degrading DC-blocking capacitors required by single-ended amplifiers. 7.2 Power Dissipation and Heat Sinking Normally, the devices dissipate a significant amount of power. The maximum power dissipation is given in Table 1 as Continuous Power Dissipation, or it can be calculated by: where TJ(MAX) is +150°C, TAMB (see Table 1) is the ambient temperature, and ΘJA is the reciprocal of the derating fac- tor in °C/W as specified in Table 1. For example, ΘJA of the TQFN package is +59.2°C/W. The increased power delivered by a BTL configuration results in an increase in internal power dissipation versus a sin- gle-ended configuration. The maximum internal power dissipation for a given VCC and load is given by: +1 -1 VOUT(P-P) VOUT(P-P) 2 x VOUT(P-P) AVD = 2 x RIN (EQ 2) RF VRMS = 2 2 (EQ 3) VOUT(P-P) POUT = RL (EQ 4) VRMS2 PDISSPKF(MAX) = ΘJA (EQ 5) TJ(MAX) -TA PDISSPKF(MAX) = π2R L (EQ 6) 2VCC2 |
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