Electronic Components Datasheet Search |
|
FM16W08-SG Datasheet(PDF) 4 Page - Cypress Semiconductor |
|
FM16W08-SG Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 18 page FM16W08 Document Number: 001-86210 Rev. *F Page 4 of 18 Device Operation The FM16W08 is a bytewide F-RAM memory logically organized as 8,192 × 8 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. Functional operation of the F-RAM memory is the same as SRAM type devices, except the FM16W08 requires a falling edge of CE to start each memory cycle. See the Functional Truth Table on page 13 for a complete description of read and write modes. Memory Architecture Users access 8,192 memory locations, each with 8 data bits through a parallel interface. The complete 13-bit address specifies each of the 8,192 bytes uniquely. The F-RAM array is organized as 1024 rows of 8-bytes each. This row segmentation has no effect on operation, however the user can group data into blocks by its endurance characteristics as explained in the Endurance section. The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When CE is deasserted HIGH, a pre-charge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. It is the user’s responsibility to ensure that VDD remains within datasheet tolerances to prevent incorrect operation. Also proper voltage level and timing relationships between VDD and CE must be maintained during power-up and power-down events. See “Power Cycle Timing” on page 12. Memory Operation The FM16W08 is designed to operate in a manner similar to other bytewide memory products. For users familiar with BBSRAM, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. For users familiar with EEPROM, the differences result from the higher write performance of F-RAM technology including NoDelay writes and much higher write endurance. Read Operation A read operation begins on the falling edge of CE. At this time, the address bits are latched and a memory cycle is initiated. Once started, a full memory cycle must be completed internally even if CE goes inactive. Data becomes available on the bus after the access time is met. After the address has been latched, the address value may be changed upon satisfying the hold time parameter. Unlike an SRAM, changing address values will have no effect on the memory operation after the address is latched. The FM16W08 will drive the data bus when OE is asserted LOW and the memory access time is met. If OE is asserted after the memory access time is met, the data bus will be driven with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven to the bus. When OE is deasserted HIGH, the data bus will remain in a HI-Z state. Write Operation In the FM16W08, writes occur in the same interval as reads. The FM16W08 supports both CE and WE controlled write cycles. In both cases, the address is latched on the falling edge of CE. In a CE-controlled write, the WE signal is asserted before beginning the memory cycle. That is, WE is LOW when the device is activated with the chip enable. In this case, the device begins the memory cycle as a write. The FM16W08 will not drive the data bus regardless of the state of OE. In a WE-controlled write, the memory cycle begins on the falling edge of CE. The WE signal falls after the falling edge of CE. Therefore, the memory cycle begins as a read. The data bus will be driven according to the state of OE until WE falls. The CE and WE controlled write timing cases are shown in the page 11 and page 12. Write access to the array begins asynchronously after the memory cycle is initiated. The write access terminates on the rising edge of WE or CE, whichever comes first. A valid write operation requires the user to meet the access time specification before deasserting WE or CE. The data setup time indicates the interval during which data cannot change before the end of the write access. Unlike other nonvolatile memory technologies, there is no write delay with F-RAM. Because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Pre-charge Operation The pre-charge operation is an internal condition in which the memory state is prepared for a new access. All memory cycles consist of a memory access and a pre-charge. Pre-charge is user-initiated by driving the CE signal HIGH. It must remain HIGH for at least the minimum pre-charge time, tPC. The user determines the beginning of this operation since a pre-charge will not begin until CE rises. However, the device has a maximum CE LOW time specification that must be satisfied. Endurance Internally, a F-RAM operates with a read and restore mechanism. Therefore, each read and write cycle involves a change of state. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM16W08, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently |
Similar Part No. - FM16W08-SG |
|
Similar Description - FM16W08-SG |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |