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LM12434CIWM Datasheet(PDF) 55 Page - National Semiconductor (TI) |
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LM12434CIWM Datasheet(HTML) 55 Page - National Semiconductor (TI) |
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55 / 80 page  70 Digital Interface (Continued) 72 8051 INTERFACE MODE The 8051 interface mode is designed to work directly with the 8051 family of microcontrollers’ mode 0 serial interface This interface mode is a simple shift register type of serial data transfer The serial clock synchronizes the transfer of data to and from the LM12434 and LM12 L 438 The inter- face uses 3 lines a bidirectional data line (RXD) a serial clock line (TXD) and a chip-select (CS) line More than one device can share the data and serial clock lines provided that each device has its own chip-select line The 8051 mode is selected when the MODESEL1 and MODESEL2 pins have the logic state of ‘‘00’’ Figure 14 shows a typical connection diagram for the 8051 mode seri- al interface The CS RXD and TXD lines are respectively assigned to interface pins P3 through P5 The P1 and P2 pins are not used in this mode and should be left open or connected to logic ‘‘1’’ In this interface the idle state of the serial clock TXD is logic ‘‘1’’ The data is stable at both edges of the TXD clock and is shifted after its rising edge The interface has a bidirectional RXD data line The LM12434 and LM12 L 438 leaves the RXD line in a high impedance state whenever it is not outputting any data Data transfer in this mode is byte oriented As mentioned the LM12434 and LM12 L 438 has three different commu- nication cycles write cycle read cycle and burst read cycle At the start of each data transfer cycle ‘‘command byte’’ is written to the LM12434 and LM12 L 438 followed by write or read data The command byte informs the LM12434 and LM12 L 438 about the communication cycle and carries the following information what type of data transfer (communication cycle) is start- ed which device register is to be accessed The command byte has the following format TLH11879 – 53 The first bit is the LSB of the byte based on the 8051 mode 0 serial interface protocol Figure 13 shows the timing diagrams for different communi- cation cycles Figure 13a shows a write cycle Figure 13b shows a read cycle Figure 13c shows a burst read cycle Note that these timing diagrams depict general relationships between the SCLK edges the data bits and CS These dia- grams are not meant to show guaranteed timing perform- ance (See specification tables for parametric switching characteristics) Write cycle A write cycle begins with the falling edge of the CS Then a command byte is written to the DAS on the RXD line synchronized by TXD clock The command byte has the RW and B bits equal to zero Following the command byte 16 bits of data (2 bytes) is shifted in on the RXD line The data is written to the register addressed in the command byte (A3 A2 A1 A0) The data is always LSB first in this interface CS will go high after the transfer of the last bit thus completing the write cycle Read cycle A read cycle starts the same way as a write cycle except that the command bytes RW bit is equal to one Following the command byte the DAS outputs the data on the RXD line synchronized with the microcontrol- ler’s TXD clock The data is read from the register ad- dressed in the command byte Data is shifted in LSB first Again CS will go high after the transfer of the last data bit thus completing the read cycle 55 |
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