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TC94A29FB Datasheet(PDF) 8 Page - Toshiba Semiconductor |
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TC94A29FB Datasheet(HTML) 8 Page - Toshiba Semiconductor |
8 / 20 page TC94A29FAG/FB 2003-04-01 8 Pin No. Symbol Pin Name Function and Operation Remarks 10 P1-0/SCK1 /RX1 /CTin /DATA (BRK10) I/O port 1-0 /serial clock input/output 1 /serial receive data 1 /counter clock input /CD processor function 11 P1-1/SDIO1 /TX1 /SFSY (BRK11) I/O port 1-1 /serial data input/output 1 /serial transmit data 1 /CD processor function 12 P1-2/SI1 /SBSY (BRK12) I/O port 1-2 /serial data input 1 /CD processor function 13 P1-3/BUZR (BRK13) I/O port 1-3 /buzzer output 14 P7-0/SCK2 /RX2 (BRK14) I/O port 7-0 /serial clock input/output 2 /serial receive data 2 15 P7-1/SDIO2 /TX2 (BRK15) I/O port 7-1 /serial data input/output 2 /serial transmit data 2 16 P7-2/INTR /SI2 (BRK16) I/O port 7-2 /interrupt input /serial data input 2 The P1-0 pin has multiplexed functions for general-purpose counter input. The input frequency is 0.1 MHz to 20 MHz. The counter incorporates an input amplifier and operates with capacitance-coupled small amplitudes. The counter is a 20-bit counter and can store 20-bit data directly in memory. The gate time can be selected from among 1 ms, 4 ms, 16 ms and 64 ms (when the 75-kHz crystal oscillator is used). In manual mode, the gate can be turned on and off within the specified time using instructions. The P1-0 to P1-2 and P7-0 to P7-2 pins have multiplexed functions for serial interface (SIO) circuit input/output pins. The SIO is a serial interface supporting 2-line and 3-line methods as well as UART. The TC94A29FAG/FB has CMOS input/output pins (SCK1/RX1, SDIO1/TX1, SI1) and N-channel open-drain (supporting up to 5.5 V) input/output pins (SCK2/RX2, SDIO2/TX2, SI2). One of the two sets of pins can be selected as serial interface. The serial interface circuit supports various options, including the number of the clock edge to be used, the serial clock input/output, and the clock frequency. These options facilitate controlling the LSI and communications between the controllers. When SIO interrupts are enabled, an interrupt is generated as soon as execution of the SIO completes, causing the program to jump to address 4. The P1-3 pin has multiplexed functions for a buzzer output pin. One of four frequencies within the range from 0.75 kHz, 1 kHz, 1.5 kHz and 3 kHz can be selected for buzzer output (when the 75-kHz clock is used). The buzzer is driven at the selected frequency in one of four modes: continuous, single-shot, 10-Hz intermittent, and 10-Hz intermittent at 1-Hz intervals. The P7-2 pin has multiplexed functions for an external interrupt input pin. When interrupts are enabled and a pulse of 1.65 ms to 4.96 ms or more (13.3 ms to 40 ms when the 75-kHz clock is used) is applied to this pin, an interrupt is generated and the program jumps to address 1. The input logic and rising/falling edge can be selected for interrupt inputs. This input can be applied as the clock gate signal to the internal 8-bit timer/counter, which allows input pulse width to be detected and measured. (Note) Backup release is enabled or disabled in port units. (Note) Upon a system reset, the pins are set to I/O port input. (Note) When the 32.768-kHz crystal oscillator or the CR oscillator is used, the general-purpose counter is used as a timer. MVDD Input instruction Release enable MVSS RfIN CTin MVDD MVSS (When P1-0 is used for general-purpose counter) MVDD MVDD Input instruction Release enable MVSS (When used for I/O port) |
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