IC61LV6416

Integrated Circuit Solution Inc.

7

AHSR026-0A

09/12/2001

1

2

3

4

5

6

7

8

9

10

11

12

-8

-10

-12

-15

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

8

—

10

—

12

—

15

—

ns

CE to Write End

7

—

8

—

9

—

10

—

ns

Address Setup Time

7

—

8

—

9

—

10

—

ns

to Write End

Address Hold from Write End

0

—

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

0

—

ns

LB, UB Valid to End of Write

7

—

8

—

9

—

10

—

ns

WE Pulse Width

7

—

8

—

9

—

10

—

ns

Data Setup to Write End

4.5

—

5

—

6

—

7

—

ns

Data Hold from Write End

0

—

0

—

0

—

0

—

ns

—

4

—

5

—

6

—

7

ns

3

—

3

—

3

—

3

—

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and UB or LB, and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the write.