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P3Z22V10-BD Datasheet(PDF) 10 Page - NXP Semiconductors |
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P3Z22V10-BD Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 16 page Philips Semiconductors Product specification P3Z22V10 3V zero power, TotalCMOS ™, universal PLD device 1997 Jul 18 10 DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40 °C ≤ Tamb ≤ +85°C; 3.0 ≤ VDD ≤ 3.6V SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITS SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNITS VIL Input voltage low VDD = 3.0V 0.8 V VIH Input voltage high VDD = 3.6V 2 V VI Input clamp voltage VDD = 3.0V; IIN = –18mA –1.2 V VOL Output voltage low VDD = 3.0V; IOL = 8mA 0.5 V VOH Output voltage high VDD = 3.0V; IOH = –4mA 2.4 V II Input leakage current VIN = 0 to VDD –10 10 µA II In ut leakage current VIN = VDD to 5.5V2 –10 10 µA IOZ 3-Stated output leakage current VIN = 0 to VDD –10 10 µA IOZ 3-Stated out ut leakage current VIN = VDD to 5.5V2 –10 10 µA IDDQ Standby current VDD = 3.6V; Tamb = –40°C 30 45 µA IDDD 1 Dynamic current VDD = 3.6V; Tamb = –40°C @ 1MHz .5 3 mA IDDD 1 Dynamic current VDD = 3.6V; Tamb = –40°C @ 50MHz 10 20 mA ISC Short circuit output current 1 pin/time for no longer than 1 se- cond –15 –100 mA CIN Input pin capacitance Tamb = 25°C; f = 1MHz 8 pF CCLK Clock input capacitance Tamb = 25°C; f = 1MHz 5 12 pF CI/O I/O pin capacitance Tamb = 25°C; f = 1MHz 10 pF NOTES: 1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be affected. 2. Does not apply to F7. AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40 °C ≤ Tamb ≤ +85°C; 3.0 ≤ VDD ≤ 3.6V SYMBOL PARAMETER LIMITS UNIT SYMBOL PARAMETER MIN. MAX. UNIT tPD Input or feedback to non-registered output 15 ns tSU Setup time from input, feedback or SP to Clock 5 ns tCO Clock to output 10.5 ns tCF Clock to feedback1 6 ns tH Hold time 0 ns tAR Asynchronous Reset to registered output 17 ns tARW Asynchronous Reset width 5 ns tARR Asynchronous Reset recovery time 6 ns tSPR Synchronous Preset recovery time 6 ns tWL Width of Clock LOW 3 ns tWH Width of Clock HIGH 3 ns tR Input rise time 20 ns tF Input fall time 20 ns fMAX1 Maximum internal frequency2 (1/tSU + tCF) 91 MHz fMAX2 Maximum external frequency1 (1/tSU + tCO) 65 MHz fMAX3 Maximum clock frequency1 (1/tWL + tWH) 167 MHz tEA Input to Output Enable 11 ns tER Input to Output Disable 11 ns Capacitance CIN Input pin capacitance 10 pF COUT Output capacitance 12 pF NOTES: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. |
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