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W65C02S6PL-14 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers |
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W65C02S6PL-14 Datasheet(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 40 page The Western Design Center, Inc. W65C02S Data Sheet The Western Design Center, Inc. W65C02S Data Sheet 11 3.11 Reset (RESB) The Reset (RESB) input is used to initialize the microprocessor and start program execution. The RESB signal must be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY) has no effect while RESB is being held low. All Registers are initialized by software except the Decimal and Interrupt disable mode select bits of the Processor Status Register (P) are initialized by hardware. When a positive edge is detected, there will be a reset sequence lasting seven clock cycles. The program counter is loaded with the reset vector from locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. RESB should be held high after reset for normal operation. Processor Status Register (P) 7 6 5 4 3 2 1 0 * * 1 1 0 1 * * N V B D I Z C *=software initialized 3.12 Set Overflow (SOB) A negative transition on the Set Overflow (SOB) pin sets the overflow bit (V) in the status code register. The signal is sampled on the rising edge of PHI2. SOB was originally intended for fast input recognition because it can be tested with a branch instruction; however, it is not recommended in new system design and was seldom used in the past. 3.13 SYNChronize with OpCode fetch (SYNC) The OpCode fetch cycle of the microprocessor instruction is indicated with SYNC high. The SYNC output is provided to identify those cycles during which the microprocessor is fetching an OpCode. The SYNC line goes high during the clock cycle of an OpCode fetch and stays high for the entire cycle. If the RDY line is pulled low during the clock cycle in which SYNC went high, the processor will stop in its current state and will remain in the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause single instruction execution. 3.14 Power (VDD) and Ground (VSS) VDD is the positive power supply voltage and VSS is system logic ground. 3.15 Vector Pull (VPB) The Vector Pull (VPB) output indicates that a vector location is being addressed during an interrupt sequence. VPB is low during the last interrupt sequence cycles, during which time the processor reads the interrupt vector. The VPB signal may be used to select and prioritize interrupts from several sources by modifying the vector addresses. |
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