ACT510x

Rev 1.0, 04-Apr-2018

16

Table 4: STAT pin State

State

STAT Output Pin

Converter Enabled and Output Valid

LOW

Converter Disabled

HIZ

Converter Enabled but in Fault, Hiccup or Light Load states

HIZ

6. Interrupt Output Pin (nIRQ)

The nIRQ output pin can be used to signal a fault or other system effects. The conditions below can active the nIRQ Pin

and all of them can be masked individually using the IRQ Control Registers 0x1E and 0x1F. To clear the nIRQ and de-

assert the nIRQ pin, the nIRQ_CLEAR must be written to a 1. The nIRQ_CLEAR is a self-clearing register bit. If the

nIRQ_CLEAR is read, it will always be a 0, even if it has been written to 1.

1.

Watchdog Expired - If the watchdog timer expires at any time, it will active the nIRQ Pin. This is level sensitive

function. The watchdog timer must be reset or disabled and nIRQ_CLEAR must be written to 1 for the nIRQ to be

de-asserted. – No watchdog in HIZ so cannot be triggered HIZ mode.

2. VREG LDO Overcurrent or Under-voltage Lockout- Any time the VREG LDO is in overcurrent or under-voltage

lockout, the nIRQ will be asserted. This is a level sensitive function. The VREG LDO must be in regulation AND

nIRQ_CLEAR must be written to a 1 for nIRQ to be de-asserted. If the VREG LDO is in the 100msec shutdown

wait period, it will not clear the nIRQ output. This fault WILL be valid in all modes, including HIZ Mode.

will be asserted.

This is a level sensitive function.

nIRQ_CLEAR must be written to 1 for nIRQ to be de-asserted.

4. FET Overcurrent Fault – If the device is disabled from switching because of FET overcurrent fault, the nIRQ will

be asserted. This is a level sensitive function. This fault is latched, so the latch must cleared AND nIRQ_CLEAR

must be written to 1 for nIRQ to be de-asserted.

5. A2D Data Ready – If the A2D is enabled, and a conversion is completed the nIRQ pin will be asserted. This is an

edge triggered event and only a write to1 of nIRQ_CLEAR is needed to de-assert the nIRQ pin. This can be active

in all modes, when the A2D is enabled.

6. HIZ Enter – If the devices enters HIZ mode the nIRQ pin will be asserted. This is an edge triggered event and only

a write to 1 of the nIRQ_CLEAR is needed to de-assert the nIRQ pin. This is used to signal a fault or other condition

that might have caused the device to jump out of operation mode un-expectantly.

7. I2C Fault – If the I2C command requires more than 100msec to complete, then a fault is latched on the rising edge

of the error. This fault will get reset when another I2C command completes correctly, but is latched with the Reg

0x06 Bit 1.

function.

10. VIN UV - Any time the VIN is below VIN_UV threshold, the nIRQ will be asserted. This is a level sensitive function.

VIN must be in the valid range AND nIRQ_CLEAR must be written to 1 for nIRQ to be de-asserted.

11. Light Load Disable State - Any time the device enters the LL_DIS state, the nIRQ will be asserted until the

nIRQ_CLEAR Register is written to 1. The nIRQ is triggered with a “rising edge” of the LL_DIS state and does not

require exiting the state to de-assert the nIRQ pin.

12. Hiccup Mode / Vout Fault State - Any time the device enters the HICCUP state, the nIRQ will be asserted until the

nIRQ_CLEAR Register is written to 1. The nIRQ is triggered with a “rising edge” of the HICCUP state and does not

require exiting the state to de-assert the nIRQ pin.