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ACT2861QI Datasheet(PDF) 47 Page - Active-Semi, Inc |
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ACT2861QI Datasheet(HTML) 47 Page - Active-Semi, Inc |
47 / 91 page ACT2861QI Rev 2.0, 27-Apr-2018 Innovative PowerTM www.active-semi.com ActiveSwitcherTM is a trademark of Active-Semi Copyright © 2018 Active-Semi, Inc. 47 Table 9: OTG Inductor and Compensation ICOMP RICOMP1 CICOMP1 CICOMP2 Figure 16: OTG Compensation CHARGE STATUS OUTPUT PIN (NCHG) The ACT2861 indicates the Charging and OTG states on the open drain nCHG pin. The nCHG pin typically drives an LED, but can also be monitored by a micro- processor GPIO. In Charge mode, the nCHG pin func- tion is enabled by setting I2C bit DIS_nCHG_CHG in register 0x00h = 0. Disable the function by setting it to 1. In OTG mode, the nCHG function is enabled by set- ting the I2C bit EN_OTG_nCHG in register 0x0Fh = 1. Disable the function by setting it to 0. Tables 10 and 11 show the nCHG state in different Charge and OTG operating conditions. Table 10: nCHG Pin State in Charge Mode Charging State nCHG Output Pin Charging in progress LOW Charging complete HIZ Charge suspend or Fault Blinking at 1Hz Table 11: nCHG Pin State in OTG Mode OTG State nCHG Output Pin OTG Enabled and Output Valid LOW OTG Disabled HIZ OTG Enabled In Fault, Hiccup, or Light Load states HIZ ADC Monitoring General Description The ACT2861 contains a built-in analog to digital con- verter, ADC, which can be used to monitor seven sys- tem level parameters. These include input voltage, out- put voltage, input current, output current, TH pin, die temperature, and the external ADC input pin. It uses a single 12 bit delta-sigma ADC that uses an analog input multiplexer to select one of seven channels for the A/D conversion. The resulting digital results are stored in seven digital registers. A seven to one multiplexer con- nects one of the ADC output registers to the user ac- cessible register map. ADC Configuration The ACT2861 ADC is configured through the I2C inter- face. It is enabled and disabled by the I2C bit EN_ADC in register 0x09h. The ADC has two conversion modes, manual single-shot conversion and automatic polling conversion. Single-Shot Conversion Configure the IC for single-shot conversion mode by setting the following I2C bits in register 0x09h Standard Capacitance Design Minimum Capacitance Design Switching Frequency Inductor Min / Typ / Max (uH) CICOMP1 (nF) CICOMP2 (nF) RICOMP (kΩ) Ceramic Capacitor (uF) Bulk Capacitor (uF) Bulk Capacitor ESR (mΩ) Ceramic Capacitor (uF) Bulk Capacitor (uF) Bulk Capacitor ESR (mΩ) 125Khz 29 / 42 / 55 82 8.2 20.0 47 1000 N/A 22 470 30 - 100 250Khz 15 / 22 / 29 39 3.9 20.0 47 470 N/A 22 220 50 - 200 500KHz 7 / 10 / 13 22 2.2 20.0 47 220 N/A 22 100 50 - 200 1MHZ 4 / 5.6 / 7.28 10 1.0 20.0 47 100 N/A 22 100 50 - 200 |
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