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ACT8849 Datasheet(PDF) 28 Page - Active-Semi, Inc |
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ACT8849 Datasheet(HTML) 28 Page - Active-Semi, Inc |
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28 / 35 page  ACT8849 Rev PrB, 12-Jun-14 Innovative PowerTM - 28 - www.active-semi.com Copyright © 2014 Active-Semi, Inc. Active-Semi Confidential―Do Not Copy or Distribute ActivePMU TM is a trademark of Active-Semi. I2CTM is a trademark of NXP. Push-Button Control The ACT8849 is designed to initiate a system enable sequence when the nPBIN multi-function input is asserted. Once this occurs, a power-on sequence commences, as described below. The power-on sequence must complete and the microprocessor must take control (by asserting PWRHLD) before nPBIN is de-asserted. If the microprocessor is unable to complete its power-up routine successfully before the user releases the push-button, the ACT8849 automatically shuts the system down. This provides protection against accidental or momentary assertions of the push- button. If desired, longer “push-and-hold” times can be implemented by simply adding an additional time delay before asserting PWREN or PWRHLD. Control Sequences The ACT8849 features a variety of control sequences that are optimized for supporting system enable and disable, as well as SLEEP mode of the Samsung Exynos4412 processors. Enabling/Disabling Sequence A typical enable sequence is initiated whenever the nPBIN is asserted low via 50KΩ resistance. The power control diagram is shown in Figure 3. During the boot sequence, the microprocessor must assert PWRHLD ( XPSHO L D) , and PWREN (XPWRRGTON) , to ensure that the system remains powered after nPBIN is released. Once the power- up routine is completed, the system remains enabled after the push-button is released as long as PWRHLD is asserted high. If the processor does not assert PWRHLD before the user releases the push-button, the boot-up sequence is terminated and all regulators are disabled. This provides protection against "false-enable", when the push- button is accidentally depressed, and also ensures that the system remains enabled only if the processor successfully completes the boot-up sequence. As with the enable sequence, a typical disable sequence is initiated when the user presses the push-button, which interrupts the processor via the nPBSTAT output. The actual disable sequence is completely software-controlled, but typically involved initiating various “clean-up” processes before the processor finally de-asserts PWRHLD. SLEEP Mode Sequence The ACT8849 supports Exynos4412 processors’ SLEEP mode operation. Once a successful power- up routine has been completed, SLEEP mode may be initiated through a variety of software-controlled mechanisms. SLEEP mode is typically initiated when the user presses the push-button during normal operation. Pressing the push-button asserts the nPBIN input, which asserts the nPBSTAT output, which interrupts the processor. In response to this interrupt the processor should de-assert PWRE N (XPWRR GT ON) , di sa bli ng REG6/7/8/9/10/11/12. PWRHLD should remain asserted during SLEEP mode so that REG1/6/7/12 remain enabled. The ACT8849 wakes up from SLEEP mode when either the push-button and/or PWREN (XPWRRGTON) is asserted. In either case, REG2/3/4/5/8/9/10/11 are enable which allow the system to resume normal operation. Watch-Dog Supervision The ACT8849 features a watchdog supervisory function. An internal watchdog timer of 4s is unmasked by setting either WDSREN[ ] or WDPCEN [ ] bit to one. Once enabled, the watchdog timer is reset whenever there is I2C activity for the PMU. In the case where the system software stops responding and that there is no I2C transactions for 4s, the watchdog timer expires. As a result, the PMU either perform a soft-reset or power cycle, depending on whether WDSREN [ ] or WDPCEN [ ] is set. Software-Initiated Power Cycle ACT8849 supports software-initiated power cycle. Once the SIPC[ ] bit is set, the PMU waits for 8ms and then initiate a power cycle to restart the entire system. |
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