6.42

IDT70914S

High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

10

Functional Description

The IDT70914 provides a true synchronous Dual-Port Static RAM

interface. Registered inputs provide very short set-up and hold times on

address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked

on the rising edge of the clock signal. An asynchronous output enable is

provided to ease asynchronous bus interfacing.

The internal write pulse width is dependent on the LOW to HIGH

transitionsoftheclocksignalallowingtheshortestpossiblerealizedcycle

times.Clockenableinputsareprovidedtostalltheoperationoftheaddress

and data input registers without introducing clock skew for very fast

interleaved memory applications.

A HIGH on the

CE input for one clock cycle will power down the

internal circuitry to reduce static power consumption.

NOTES:

1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW

voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change

2.

3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/

W and CE are LOW, a write cycle is initiated on

the LOW-to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK.

4. The register outputs are internal signals from the register inputs being clocked in or disabled by

CLKEN.

Mode

Inputs

Register Inputs

ADDR

DATAIN

ADDR

DATAOUT

Load "1"

↑

L

HHH

H

Load "0"

↑

LLLLL

Hold (do nothing)

↑

HX

X

NC

NC

X

H

X

X

NC

NC

3490 tbl 10

Inputs

Outputs

Mode

Asynchronous

CLK

CE

R/

W

OE

↑

H

X

X

High-Z

Deselected, Power-Down

↑

LL

X

Selected and Write Enabled

↑

LH

L

Read Selected and Data Output Enable Read

↑

X

X

H

High-Z

Outputs Disabled

3490 tbl 09