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IDT70914S20P Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT70914S20P Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 11 page ©2000 Integrated Device Technology, Inc. JANUARY 2001 DSC-3490/6 1 Features x x x x x High-speed clock-to-data output times – Military: 20/25ns (max.) – Commercial: 12/15/20ns (max.) x x x x x Low-power operation – IDT70914S Active: 850 mW (typ.) Standby: 50 mW (typ.) x x x x x Architecture based on Dual-Port RAM cells – Allows full simultaneous access from both ports x x x x x Synchronous operation – 4ns setup to clock, 1ns hold on all control, data, and address inputs – Data input, address, and control registers Functional Block Diagram – Fast 12ns clock to data out – Self-timed write allows fast cycle times – 16ns cycle times, 60MHz operation x x x x x TTL-compatible, single 5V (+ 10%) power supply x x x x x Clock Enable feature x x x x x Guaranteed data output hold times x x x x x Available in 68-pin PLCC, and 80-pin TQFP x x x x x Military product compliant to MIL-PRF-38535 QML x x x x x Industrial temperature range (-40°C to +85°C) is available for selected speeds. x x x x x Recommended for replacement of IDT7099 (4K x 9) if separate 9th bit data control signals are not required. HIGH SPEED 36K (4K X 9) SYNCHRONOUS DUAL-PORT RAM IDT70914S MEMOR Y ARRAY I/O0-8L OEL CLKL CLKENL R/ WL CEL Self- timed Write Logic REG REG en REG en MEMORY ARRAY WRITE LOGIC SENSE AMPS WRITE LOGIC SENSE AMPS DECODER DECODER Self- timed Write Logic REG I/O0-8R OER CLKR CLKENR R/ WR CER 3490 drw 01 A0L-A11L A0R-A11R |
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