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IDT70914S12F Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT70914S12F Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 11 page 6.42 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 9 Timing Waveform of Read-to-Write Cycle No. 1(1,2) (tCYC = min.) Timing Waveform of Read-to-Write Cycle No. 2(4) (tCYC > min.) NOTES: 1. For tCYC = min.; data out coincident with the rising edge of the subsequent write clock can occur. To ensure writing to the correct address location, the write must be repeated on the second write clock rising edge. If CE = VIL, invalid data will be written into array. The An+1 must be rewritten on the following cycle. 2. OE LOW throughout. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. For tCYC > min.; OE may be used to avoid data out coincident with the rising edge of the subsequent write clock. Use of OE will eliminate the need for the write to be repeated. R/W ADDRESS DATAIN CE CLKEN CLK 3490 drw 11 An An + 1 tCYC tCH tH tCKLZ tCL tS Dn + 1 Qn tCD DATAOUT (3) OE tOHZ (4) R/ W ADDRESS DATAIN CE CLKEN CLK 3490 drw 10 An An + 1 An + 1 An + 2 tCYC tCH tCL tH tCKLZ tCYC tCH tCL tS Dn + 1 Dn + 2 Qn tCD tCKHZ DATAOUT (3) (3) (1) (1) (1) |
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