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LM9801CCV Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM9801CCV
Description  Greyscale/24-Bit Color Linear CCD Sensor Processor
Download  34 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM9801CCV Datasheet(HTML) 5 Page - National Semiconductor (TI)

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DC and Logic Electrical Characteristics (Continued)
The following specifications apply for AGND e DGND e DGND(IO) e 0V VA e VD ea50VDC VD(IO) ea50 or
a
30VDC REF IN ea1225VDC fMCLK e 20 MHz Rs e 25X Boldface limits apply for TA e TJ e TMIN to TMAX all
other limits TA e TJ e 25 C (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
Operating
25
32
mA (max)
Standby
50
m
A
ID
Digital Supply Current
Operating
6
8
mA (max)
MCLK e 065
m
A
ID(IO)
Digital IO Supply Current
Operating VD(IO) e 50V
31
6
mA (max)
Operating VD(IO) e 30V
16
4
mA (max)
MCLK e 0 VD(IO) e 50V or 30V
17
mA
AC Electrical Characteristics MCLK Independent
The following specifications apply for AGND e DGND e DGND(IO) e 0V VA e VD e VD(IO) ea50VDC REF IN e
a
1225VDC fMCLK e 20 MHz tMCLK e 1fMCLK tr e tf e 5 ns Rs e 25X CL (databus loading) e 50 pFpin Boldface
limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 7 and 8)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
fMCLK
Maximum MCLK Frequency
20
MHz (min)
Minimum MCLK Frequency
1
MHz (max)
MCLK Duty Cycle
30
40
% (min)
70
60
% (max)
tA
SYNC Setup of MCLK
5
10
ns (min)
tCDSETUP
Correction Data Valid to CLK Setup
14
20
ns (min)
tCDHOLD
Correction Data Valid to CLK Hold
b
12
0
ns (min)
tD1H tD0H
RD High to DD0 – DD7 TRI-STATE
5
15
ns (max)
tDACC
Access Time Delay from RD Low to
15
30
ns (max)
DD0 – DD7 Data Valid
fSCLK
Maximum SCLK Frequency
20
MHz (min)
SCLK Duty Cycle
40
% (min)
60
% (max)
tSDI
SDI Set-Up Time from SCLK
3
10
ns (min)
Rising Edge
tHDI
SDI Hold Time from SCLK
2
15
ns (min)
Rising Edge
tDDO
Delay from SCLK Falling Edge to
25
50
ns (max)
SDO Data Valid
tHDO
SDO Hold Time from SCLK
RL e 3k CL e 50 pF
30
50
ns (max)
Falling Edge
5
ns (min)
tDELAY
DELAY from SCLK Falling Edge to
5
10
ns (min)
CS Rising or Falling Edge
tSETUP
Set-Up Time of CS Rising or Falling
0
10
ns (min)
Edge to SCLK Rising Edge
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