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TPS54073 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS54073 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 23 page www.ti.com Connect Pin 1 to Analog Ground Plane in This Area for Optimum Performance Minimum Recommended Top Side Analog Ground Area 0.3478 0.0150 0.06 0.0256 0.1700 0.1340 0.0630 0.0400 Ø 0.0180 4 PL 0.2090 Ø 0.0130 8 PL Minimum Recommended Exposed Copper Area for PowerPAD. 5mm Stencils May Require 10 Percent Larger Area 0.0650 0.0500 0.0500 0.0650 0.0339 0.0339 0.0500 Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside PowerPAD Area 4 x 0.018 Diameter Under Device as Shown. Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground Area Is Extended. 0.3820 TPS54073 SLVS547 – FEBRUARY 2005 output filter capacitor(s) between the VOUT trace and For operation at full rated load current, the analog PGND. It is important to keep the loop formed by the ground plane must provide an adequate PH pins, Lout, Cout, and PGND as small as is heat-dissipating area. A 3-inch by 3-inch plane of practical. Place the compensation components from 1-ounce copper is recommended, though not manda- the VOUT trace to the VSENSE and COMP pins. Do tory, depending on ambient temperature and airflow. not place these components too close to the PH Most applications have larger areas of internal ground trace. Due to the size of the IC package and the plane available, and the PowerPAD must be connec- device pinout, they must be routed close, but main- ted to the largest area available. Additional areas on tain as much separation as possible while keeping the top or bottom layers also help dissipate heat, and the layout compact. Connect the bias capacitor from any area available must be used when 6-A or greater the VBIAS pin to analog ground using the isolated operation is desired. Connection from the exposed analog ground trace. If a slow-start capacitor or RT area of the PowerPAD to the analog ground plane resistor is used, or if the SYNC pin is used to select layer must be made using 0.013-inch diameter vias to 350-kHz operating frequency, connect them to this avoid solder wicking through the vias. trace. Eight vias must be in the PowerPAD area with four Optional prebias diodes should be connected be- additional vias located under the device package. The tween the output voltage trace and the prebias size of the vias under the package, but not in the source. The source is VIN, PVIN, or some other exposed thermal pad area, can be increased to voltage rail. This is dependent on the user's appli- 0.018. Additional vias beyond the twelve rec- cation circuit. In some cases, the diodes are not ommended that enhance thermal performance must required if the prebias voltage is caused by an be included in areas not under the device package. external load circuit leakage path. Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD 9 |
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