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AD7451 Datasheet(PDF) 6 Page - Analog Devices |
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AD7451 Datasheet(HTML) 6 Page - Analog Devices |
6 / 15 page REV. PrC PRELIMINARY TECHNICAL DATA –6– Limit at Parameter TMIN, TMAX Units Description fSCLK 4 10 kHz min 18 MHz max tCONVERT 16 x tSCLK tSCLK = 1/fSCLK 888 ns max tQUIET 25 ns min Minimum Quiet Time between the End of a Serial Read and the Next Falling Edge of CS t1 10 ns min Minimum CS Pulsewidth t2 10 ns min CS falling Edge to SCLK Falling Edge Setup Time t3 5 20 ns max Delay from CS Falling Edge Until SDATA 3-State Disabled t4 5 40 ns max Data Access Time After SCLK Falling Edge t5 0.4 tSCLK ns min SCLK High Pulse Width t6 0.4 tSCLK ns min SCLK Low Pulse Width t7 10 ns min SCLK Edge to Data Valid Hold Time t8 6 10 ns min SCLK Falling Edge to SDATA 3-State Enabled 35 ns max SCLK Falling Edge to SDATA 3-State Enabled tPOWER-UP 7 1 µs max Power-Up Time from Full Power-Down NOTES 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 Volts. 2See Figure 1, Figure 2 and the ‘Serial Interface’ section. 3Common Mode Voltage. 4Mark/Space ratio for the SCLK input is 40/60 to 60/40. 5Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross 0.4 V or 2.0 V for VDD = 3 V. 6t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num- ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 7 See ‘Power-up Time’ Section. Specifications subject to change without notice. TIMING SPECIFICATIONS 1,2 ( VDD = 2.7V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V; FIN = 300kHz; TA = TMIN to TMAX, unless otherwise noted.) Figure 1. AD7451 Serial Interface Timing Diagram Figure 2. AD7441 Serial Interface Timing Diagram AD7451/AD7441 1 2 345 13 16 15 14 t 3 00 0 0 DB11 DB10 DB2 DB1 DB0 t 2 4 LEADING ZERO’S 3-STATE t 4 t 6 t 5 t 7 t 8 t QUIET CONVERT t B +5 SCLK SDATA t 1 1 23 4 5 13 16 15 14 t 3 00 0 0 DB9 DB8 DB0 0 0 t 2 4 LEADING ZERO’S 3-STATE t 4 t 6 t 5 t 7 t 8 t QUIET CONVERT t B +5 SCLK SDATA t 1 2 TRAILING ZEROS |
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