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ADM1085 Datasheet(PDF) 9 Page - Analog Devices |
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ADM1085 Datasheet(HTML) 9 Page - Analog Devices |
9 / 16 page ADM1085/ADM1086/ADM1087/ADM1088 Rev. 0 | Page 9 of 16 CIRCUIT INFORMATION TIMING CHARACTERISTICS AND TRUTH TABLES The enable outputs of the ADM1085/ADM1086/ADM1087/ ADM1088 are related to the VIN and enable inputs by a simple AND function. The enable output is asserted only if the enable input is asserted and the voltage at VIN is above VTH_RISING, with the time delay elapsed. Table 5 and Table 6 show the enable output logic states for different VIN/enable input combinations when the capacitor delay has elapsed. The timing diagrams in Figure 18 and Figure 19 give a graphical representation of how the ADM1085/ADM1086/ADM1087/ADM1088 enable outputs respond to VIN and enable input signals. Table 5. ADM1085/ADM1086 Truth Table VIN ENIN ENOUT <VTH_FALLING 0 0 <VTH_FALLING 1 0 >VTH_RISING 0 0 >VTH_RISING 1 1 Table 6. ADM1087/ADM1088 Truth Table VIN ENIN ENOUT <VTH_FALLING 1 1 <VTH_FALLING 0 1 >VTH_RISING 1 1 >VTH_RISING 0 0 VIN ENIN ENOUT tEN VTH_RISING VTH_FALLING Figure 18. ADM1085/ADM1086 Timing Diagram VIN ENIN ENOUT tEN VTH_RISING VTH_FALLING Figure 19. ADM1087/ADM1088 Timing Diagram When VIN reaches the upper threshold voltage (VTH_RISING), an internal circuit generates a delay (tEN) before the enable output is asserted. If VIN drops below the lower threshold voltage (VTH_FALLING), the enable output is deasserted immediately. Similarly, if the enable input is disabled while VIN is above the threshold, the enable output deasserts immediately. Unlike VIN, a low-to-high transition on ENIN (or high-to-low on ENIN) does not yield a time delay on ENOUT (ENOUT). CAPACITOR-ADJUSTABLE DELAY CIRCUIT Figure 20 shows the internal circuitry used to generate the time delay on the enable output. A 250 nA current source charges a small internal parasitic capacitance, CINT. When the capacitor voltage reaches 1.2 V, the enable output is asserted. The time taken for the capacitor to reach 1.2 V, in addition to the propa- gation delay of the comparator, constitutes the enable timeout, which is typically 35 µs. To minimize the delay between VIN falling below VTH_FALLING and the enable output de-asserting, an NMOS transistor is con- nected in parallel with CINT. The output of the voltage detector is connected to the gate of this transistor so that, when VIN falls below VTH_FALLING, the transistor switches on and CINT discharges quickly. 1.2V C CINT CEXT SIGNAL FROM VOLTAGE DETECTOR TO AND GATE AND OUTPUT STAGE VCC 250nA Figure 20. Capacitor-Adjustable Delay Circuit Connecting an external capacitor to the CEXT pin delays the rise time—and therefore the enable timeout—further. The relationship between the value of the external capacitor and the resulting timeout is characterized by the following equation: tEN = (C × 4.8 ×106) + 35 µs |
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