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COPC980 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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COPC980 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 30 page  Pin Descriptions VCC and GND are the power supply pins CKI is the clock input This can come from an external source a RC generated oscillator or a crystal (in conjunc- tion with CKO) See Oscillator description RESET is the master reset input See Reset description PORT I is an 8-bit Hi-Z input port The 28-pin device does not have a full complement of Port I pins The unavailable pins are not terminated ie they are floating A read opera- tion for these unterminated pins will return unpredictable values The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations The unterminated Port I pins will draw power only when addressed PORT L is an 8-bit IO port PORT C is a 4-bit IO port Three memory locations are allocated for the L G and C ports one each for data register configuration register and the input pins Reading bits 4 – 7 of the C-Configuration reg- ister data register and input pins returns undefined data There are two registers associated with the L and C ports a data register and a configuration register Therefore each L and C IO bit can be individually configured under software control as shown below Config Data Ports L and C Setup 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output On the 28-pin part it is recommended that all bits of Port C be configured as outputs PORT G is an 8-bit port with 6 IO pins (G0 – G5) and 2 input pins (G6 G7) All eight G-pins have Schmitt Triggers on the inputs There are two registers associated with the G port a data register and a configuration register Therefore each G port bit can be individually configured under software control as shown below Config Data Port G Setup 0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output Since G6 and G7 are input only pins any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded Reading the G6 and G7 configuration bits will return zeros The device will be placed in the HALT mode by writing to the G7 bit in the G-port data register Six pins of Port G have alternate features G0 INTR (an external interrupt) G3 TIO (timercounter inputoutput) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock IO) G6 SI (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart input (general purpose input) Pins G1 and G2 currently do not have any alternate func- tions PORT D is an 8-bit output port that is preset high when RESET goes low Care must be exercised with the D2 pin operation At RESET the external loads on this pin must ensure that the output voltages stay above 09 VCC to pre- vent the chip from entering special modes Also keep the external loading on D2 to less than 1000 pF Functional Description Figure 1 shows the block diagram of the internal architec- ture Data paths are illustrated in simplified form to depict how the various logic elements communicate with each oth- er in implementing the instruction set of the device ALU AND CPU REGISTERS The ALU can do an 8-bit addition subtraction logical or shift operation in one cycle time There are five CPU registers A is the 8-bit Accumulator register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is the 8-bit address register can be auto incremented or decremented X is the 8-bit alternate address register can be incremented or decremented SP is the 8-bit stack pointer points to subroutine stack (in RAM) B X and SP registers are mapped into the on chip RAM The B and X registers are used to address the on chip RAM The SP register is used to address the stack in RAM during subroutine calls and returns PROGRAM MEMORY Program memory consists of 4096 bytes of ROM These bytes may hold program instructions or constant data The program memory is addressed by the 15-bit program coun- ter (PC) ROM can be indirectly read by the LAID instruction for table lookup DATA MEMORY The data memory address space includes on chip RAM IO and registers Data memory is addressed directly by the in- struction or indirectly by the B X and SP registers The device has 128 bytes of RAM Sixteen bytes of RAM are mapped as ‘‘registers’’ that can be loaded immediately decremented or tested Three specific registers B X and SP are mapped into this space the other bytes are available for general usage The instruction set permits any bit in memory to be set reset or tested All IO and registers (except the A PC) are memory mapped therefore IO bits and register bits can be directly and individually set reset and tested A is not mem- ory mapped but bit operations can be still performed on it Note RAM contents are undefined upon power-up RESET The RESET input when pulled low initializes the microcon- troller Initialization will occur whenever the RESET input is pulled low Upon initialization the ports L G and C are placed in the TRI-STATE mode and the Port D is set high The PC PSW and CNTRL registers are cleared The data and configuration registers for Ports L G and C are cleared The external RC network shown in Figure 4 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes http www nationalcom 11 |
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