9

510 - 78 - 06

10k

V

REG

3µ3

RF

VBIAS

13

9

57

10

11

17

6

GND

I BIAS

D

OUT

D

IN

B OUT

B

IN

OUTPUT

-

+

P GND

12

VCC

2k2

+1.3 V

S1

R IN 17

26

27

1

68n

I 10

10n

10n

68n

31

30

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Quiescent Voltage on Pad 17

V

17

-

1.2

-

V

Min Receiver Bias Voltage

V

REC MIN

I

BIAS

= 0

µA (Note 1)

-

100

-

mV

Max Receiver Bias Voltage

V

REC MAX

I

BIAS

= I

R

x 1.875 (Note 1)

-

300

-

mV

Input Resistance Pad 17

R

IN17

I

BIAS

= I

R

-

40

-

k

Ω

Internal Feedback Resistor

R

F

I

10

= I

R

-

240

-

k

Ω

Max Sinking Current (Pad 11)

I

SINK

(S1 closed)

-

10

-

mA

NOTE:

1. V

REC

= V

cc

- V

11

All switches remain as shown in the Test Circuit otherwise stated in the CONDITION column.

OUTPUT STAGE

All resistors in ohms, all capacitors in

farads, unless otherwise stated.

Fig. 14 Output Stage Test Circuit

COMMENTS:

1. Pin 23 and Pin 4 represent virtual ground inputs.

2. If the length of the wires between the current sources and the GP520A is

extensive, it may be necessary to connect an RC filter close to the

appropriate GP520A pin for noise immunity.

e.g.

I

CLIP

GP520A

4

100k

10µ

All resistors in ohms, all capacitors in

farads, unless otherwise stated.