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AK5522 Datasheet(PDF) 36 Page - Asahi Kasei Microsystems |
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AK5522 Datasheet(HTML) 36 Page - Asahi Kasei Microsystems |
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36 / 84 page  [AK5522] 017002311-E-00 2017/03 - 36 - Clock Timings (Serial Control Mode) (continued) Figure 24. Clock Timing (PLL Master Mode) Figure 25. Clock Timing (PLL Slave Mode) Audio Interface Timings (Serial Control Mode) LRCK (O) BICK (O) SDTO (O) tBSD tMBLR 50%DVDD 50%DVDD 50%DVDD tLRS Figure 26. Audio Interface Timing (PLL Master mode, External Master Mode) MCLK (O) 1/fMCLK tMCLKH tMCLKL LRCK (I) 1/fs tLRCKH tLRCKL BICK (I) tBICK tBICKH tBICKL 50%DVDD VIL max. VIH min. VIH min. VIL max. dMCLK = tMCLKH fMCLK100 [%] dLRCK = tLRCKH fs100 [%] tMCLK80 tMCLK20 80%DVDD 20%DVDD MCLK (I) 1/fMCLK tMCLKH tMCLKL LRCK (O) 1/fs tLRCKH tLRCKL BICK (O) tBICK tBICKH tBICKL 50%DVDD 50%DVDD VIH min. VIL max. dLRCK = tLRCKH fs100 [%] dBICK = tBICKH/tBICK 100 [%] |
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