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IDT72V3696 Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72V3696 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 39 page 10 COMMERCIALTEMPERATURERANGE IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF IDT72V3686L10 IDT72V3686L15 IDT72V3696L10 IDT72V3696L15 IDT72V36106L10 IDT72V36106L15 Symbol Parameter Min. Max. Min. Max. Unit tA Access Time, CLKA ↑ toA0-A35andCLKB↑ toB0-B17 2 6.5 2 10 ns tWFF Propagation Delay Time, CLKA ↑ to FFA/IRA and CLKC↑ to 2 6.5 2 8 ns FFC/IRC tREF Propagation Delay Time, CLKA ↑ to EFA/ORA and CLKB↑ to 1 6.5 1 8 ns EFB/ORB tPAE Propagation Delay Time, CLKA ↑ to AEAand CLKB↑ to AEB 1 6.5 1 8 ns tPAF Propagation Delay Time, CLKA ↑ to AFA and CLKC↑ to AFC 1 6.5 1 8 ns tPMF Propagation Delay Time, CLKA ↑ to MBF1 LOW or MBF2 0 6.5 0 8 ns HIGH, CLKB ↑ to MBF1 HIGH, and CLKC↑ to MBF2 LOW tPMR Propagation Delay Time, CLKA ↑ to B0-B17(1)and CLKC↑ 2 6.5 2 10 ns to A0-A35(2) tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to 2 8 2 10 ns B0-B17 valid tRSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB 110 1 15 ns LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2 HIGH tEN Enable Time, CSA or W/RA LOW to A0-A35 Active and 2 6 2 10 ns CSB LOW to B0-B17 Active tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high 1 6 1 8 ns impedance and CSB HIGH to B0-B17 at HIGH impedance NOTES: 1. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 3. Vcc = 3.3V ± 0.15V; TA = 0° to +70°. (Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant) |
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