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BTS7020-2EPA Datasheet(PDF) 35 Page - Infineon Technologies AG |
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BTS7020-2EPA Datasheet(HTML) 35 Page - Infineon Technologies AG |
35 / 58 page Data Sheet 35 Rev. 1.00 2017-08-24 BTS7020-2EPA PROFETTM+2 Protection It is possible to “force” a reset of the internal counter without waiting for tDELAY(CR) by applying a pulse (rising edge followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a duration longer than tDEN(CR) to ensure a reset of the internal counter. The DSEL pin must select the channel that has to be de-latched and keep the same logic value while DEN pin toggles twice (rising edge followed by a falling edge). The timings are shown in Figure 30. Figure 30 Retry Strategy Timing Diagram with Forced Reset 8.4 Additional protections 8.4.1 Reverse Polarity Protection In Reverse Polarity condition (also known as Reverse Battery), the output stages are switched ON (see parameter RDS(REV)) because of ReverSave™ feature which limits the power dissipation in the output stages. Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output stages must be limited by the connected loads. The current through digital input pins has to be limited as well by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in Chapter 10). Figure 31 shows a typical application including a device with ReverSave™. A current flowing into GND pin (- IGND) during Reverse Polarity condition is necessary to activate ReverSave™, therefore a resistive path between module ground and device GND pin must be present. t IN Short circu it to ground IL 0 1 Internal counter nRETRY(CR) t t t Protection_PROFET_DENforce_time2.emf DEN nRETRY(CR) 1 t tDEN(CR) 0 tDEN(CR) nRETRY(CR) tDEN(CR) nRETRY(CR) 0 |
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