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FAN3111 Datasheet(PDF) 13 Page - ON Semiconductor |
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FAN3111 Datasheet(HTML) 13 Page - ON Semiconductor |
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13 / 19 page  © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3111 • Rev. 1.6 12 Applications Information The FAN3111 offers CMOS- or logic-level-compatible input thresholds. In the FAN3111C, the logic input thresholds are dependent on the VDD level and, with VDD of 12 V, the logic rising-edge threshold is approximately 55% of VDD and the input falling-edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input-voltage hysteresis window. This allows setting precise timing intervals by fitting an R-C circuit between the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal and the OUT pin of the driver. In the FAN3111E, the input thresholds are dependent on the VXREF voltage that typically is chosen between 2V and 5 V. This range of VXREF allows compatibility with TTL and other logic levels up to 5 V by connecting the XREF pin to the same source as the logic circuit that drives the FAN3111E input stage. The logic rising edge threshold is approximately 50% of VXREF and the input falling-edge threshold is approximately 30% of VXREF. The TTL-like input configuration offers a hysteresis voltage of approximately 20% of VXREF. Startup Operation The FAN3111 internal logic is optimized to drive ground referenced N-channel MOSFETs as VDD supply voltage rises during startup operation. As VDD rises from 0V to approximately 2 V, the OUT pin is held LOW by an internal resistor, regardless of the state of the input pins. When the internal circuitry becomes active at approximately 2 V, the output assumes the state commanded by the inputs. Figure 35 illustrates FAN3111C startup operation with VDD increasing from 0 to 12 V, with the output commanded to the low level (IN+ and IN- tied to ground). Note that OUT is held LOW to maintain an N- channel MOSFET in the OFF state. OUT @ 5 V/Div VDD @ 5 V/Div t = 200 us/Div VDD OUT FAN3111C Figure 35. FAN3111C Startup Operation Figure 36 illustrates startup operation as VDD increases from 0 to 12 V with the output commanded to the high level (IN+ tied to VDD, IN- tied to GND). This configuration might not be suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would attempt to turn the P-channel MOSFET on with low VDD levels. OUT @ 5 V/Div VDD @ 5 V/Div VDD OUT FAN3111C t = 200 us/Div Figure 36. Startup Operation as VDD Increases Figure 37 illustrates FAN3111E startup operation with the output commanded to the low level (IN+ tied to ground) and the voltage on XREF ramped from 0 to 3.3 V. t = 50 us/Div OUT @ 2 V/Div VXREF @ 2 V/Div VDD @ 5 V/Div VDD OUT FAN3111E XREF Figure 37. FAN3111E Startup Operation MillerDrive™ Gate Drive Technology FAN3111 drivers incorporate the MillerDrive architecture shown in Figure 38 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a wide range of supply- voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive architecture is to speed up switching by providing the highest current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. |
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