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IS61C12816-12TI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS61C12816-12TI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 8 page IS61C12816 ISSI® Integrated Silicon Solution, Inc. — 1-800-379-4774 1 Rev. A 12/19/00 FEATURES • High-speed access time: 12, 15, and 20 ns • CMOS low power operation — 450 mW (typical) operating — 250 µW (typical) standby • TTL compatible interface levels • Single 5V ± 10% power supply • Fully static operation: no clock or refresh required • Three state outputs • Industrial temperature available • Available in 44-pin SOJ package and 44-pin TSOP(II) 128K x 16 HIGH-SPEED CMOS STATIC RAM DESCRIPTION The ISSI IS61C12816 is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design tech- niques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable ( WE) controls both writing and reading of the memory.A data byte allows Upper Byte ( UB) and Lower Byte (LB) access. The IS61C12816 is packaged in the JEDEC standard 44-pin 400-mil SOJ and 44-pin TSOP (II). FUNCTIONAL BLOCK DIAGRAM DECEMBER 2000 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. A0-A16 CE OE WE 128K x 16 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VCC I/O DATA CIRCUIT I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte UB LB |
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