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ISL6115ACBZ Datasheet(PDF) 6 Page - Renesas Technology Corp |
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ISL6115ACBZ Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 10 page  ISL6115A FN6855 Rev 1.00 Page 6 of 10 April 23, 2010 Upon a UV condition, the PGOOD signal will pull low when connected through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch-off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.8V to VDD once the time-out period expires. See Figures 2 through 13 for graphs and waveforms related to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high. Application Considerations Design applications where the CR Vth is set extremely low (25mV or less), there is a two-fold risk to consider. • There is the susceptibility to noise influencing the absolute CR Vth value. This can be addressed with a 100pF capacitor across the RSENSE resistor. • Due to common mode limitations of the overcurrent comparator, the voltage on the ISET pin must be 20mV above the IC ground either initially (from ISET*RSET) or before CTIM reaches time-out (from gate charge-up). If this does not happen, the IC may incorrectly report overcurrent fault at start-up when there is no fault. Circuits with high load capacitance and initially low load current are susceptible to this type of unexpected behavior. Do not signal nor pull-up the PWRON input to > 5V. Exceeding 6V on this pin will cause the internal charge pump to malfunction. During the soft-start and the time-out delay duration with the IC in its current limit mode, the VGS of the external N-Channel MOSFET is reduced driving the MOSFET switch into a (linear region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer’s data sheet. When driving particularly large capacitive loads a longer soft-start time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1). . CORRECT TO ISEN AND CURRENT SENSE RESISTOR INCORRECT FIGURE 1. SENSE RESISTOR PCB LAYOUT RISET |
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