ISL6532

FN9112 Rev 4.00

Page 8 of 15

Sep 12, 2013

system enters S0/S1. None of the regulators will begin the soft

start procedure until the 5V Standby bus has exceeded POR,

trip level.

Once all of these conditions are met, the PWM error amplifier

will first be reset by internally shorting the COMP pin to the FB

pin. This reset lasts for 2048 clock cycles which is typically

sequence will then begin.

The PWM error amplifier reference input is clamped to a level

proportional to the soft-start voltage. As the soft-start voltage

slews up, the PWM comparator generates PHASE pulses of

increasing width that charge the output capacitor(s). The internal

output of the PWM regulator. The soft start lasts for 2048 clock

cycles, which is typically 8.2ms. This method provides a rapid and

controlled output voltage rise.

Figure 1 shows the soft start sequence for a typical cold start.

rounded features at the start and end of the soft start whereas

ramp up.

By directly monitoring 12VATX and the SLP_S3 and SLP_S5

signals, the ISL6532 can achieve PGOOD status significantly

faster than other devices that depend on the

Latched_Backfeed_Cut signal for timing.

Active to Sleep (S0 to S3 Transition)

When SLP_S3 goes LOW with SLP_S5 still HIGH, the

regulator will be disabled. NCH is pulled low to disable the

backfeed blocking MOSFET. PGOOD will also transition LOW.

depend on the leakage characteristics of the memory and

bleed down to 0V.

regulator is immediately enabled. The switching regulator is

disabled synchronous to the switching waveform. The shut off

time will range between 4 and 8µs. The standby LDO is

capable of supporting up to 650mA of load with P5VSBY tied

to the 5V Standby Rail. The standby LDO may receive input

from either the 3.3V Standby rail or the 5V Standby rail through

the P5VSBY pin. It is recommended that the 5V Standby rail

be used as the current delivery capability of the LDO is greater.

Sleep to Active (S3 to S0 Transition)

When SLP_S3 transitions from LOW to HIGH with SLP_S5

held HIGH and after the 12V rail exceeds POR, the ISL6532

to a high impedance state turning on the blocking MOSFET.

is released. Upon release of the short, the capacitor on

VREF_IN is then charged up through the internal resistor

charge-up, acting as the S3 to S0 transition soft start for the

clock cycles, or typically 8.2ms, have passed following the S3

transition to a HIGH state.

Figure 2 illustrates a typical state transition from S3 to S0. It

output will vary according to the value of the capacitor on the

VREF_IN pin.

FIGURE 1. TYPICAL COLD START

12VATX 2V/DIV

5VSBY

S3

S5

1V/DIV

500mV/DIV

500mV/DIV

PGOOD

5V/DIV

12V POR

SOFT START

INITIATES

SOFT START ENDS

PGOOD COMPARATOR

ENABLED

2048 CLOCK

CYCLES

2048 CLOCK

CYCLES

FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION

12VATX 2V/DIV

S3

S5

500mV/DIV

500mV/DIV

PGOOD

5V/DIV

12V POR

PGOOD COMPARATOR

ENABLED

2048 CLOCK

CYCLES