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ISL6721ABZ Datasheet(PDF) 10 Page - Renesas Technology Corp |
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ISL6721ABZ Datasheet(HTML) 10 Page - Renesas Technology Corp |
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10 / 23 page  ISL6721 FN9110 Rev 9.00 Page 10 of 23 May 20, 2016 Pin Descriptions SLOPE - Means by which the ISENSE ramp slope may be increased for improved noise immunity or improved control loop stability for duty cycles greater than 50%. An internal current source charges an external capacitor to GND during each switching cycle. The resulting ramp is scaled and added to the ISENSE signal. SYNC - A bidirectional synchronization signal used to coordinate the switching frequency of multiple units. Synchronization may be achieved by connecting the SYNC signal of each unit together or by using an external master clock signal. The oscillator timing capacitor, CT, is still required, even if an external clock is used. The first unit to assert this signal assumes control. RTCT - This is the oscillator timing control pin. The operational frequency and maximum duty cycle are set by connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to LGND. The oscillator produces a sawtooth waveform with a programmable frequency range of 100kHz to 1.0MHz. The charge time, tC, the discharge time, tD, the switching frequency, fsw, and the maximum duty cycle, Dmax, can be calculated from Equations 1, 2, 3 and 4: Figure 7 may be used as a guideline in selecting the capacitor and resistor values required for a given frequency. COMP - COMP is the output of the error amplifier and the input of the PWM comparator. The control loop frequency compensation network is connected between the COMP and FB pins. The ISL6721 features a built-in full cycle soft-start. Soft-start is implemented as a clamp on the maximum COMP voltage. FB - Feedback voltage input connected to the inverting input of the error amplifier. The noninverting input of the error amplifier is internally tied to a reference voltage. Current sense leading edge blanking is disabled when the FB input is less than 2.0V. OV - Overvoltage monitor input pin. This signal is compared to an internal 2.5V reference to detect an overvoltage condition. UV - Undervoltage monitor input pin. This signal is compared to an internal 1.45V reference to detect an undervoltage condition. ISENSE - This is the input to the current sense comparators. The IC has two current sensing comparators, a PWM comparator for peak current mode control, and an overcurrent protection comparator. The overcurrent comparator threshold is adjustable through the ISET pin. Exceeding the overcurrent threshold will start a delayed shutdown sequence. Once an overcurrent condition is detected, the soft-start charge current source is disabled and a discharge current source is enabled. The soft-start capacitor begins discharging, and if it discharges to less than 4.375V (sustained overcurrent threshold), a shutdown condition occurs and the GATE output is forced low. See “Overcurrent Operation” on page 12 for more details. The GATE output remains low until the reset threshold is attained. At this point, a soft-start cycle begins. If the overcurrent condition ceases, and then an additional 50µs period elapses before the shutdown threshold is reached, no shutdown occurs and the soft-start voltage is allowed to recharge. LGND - LGND is a small signal reference ground for all analog functions on this device. PGND - This pin provides a dedicated ground for the output gate driver. The LGND and PGND pins should be connected externally using a short printed circuit board trace close to the IC. This is imperative to prevent large, high frequency switching currents flowing through the ground metallization inside the IC. (Decouple VC to PGND with a low ESR 0.1µF or larger capacitor.) GATE - This is the device output. It is a high current power driver capable of driving the gate of a power MOSFET with peak currents of 1.0A. This GATE output is actively held low when VCC is below the UVLO threshold. The output high voltage is clamped to ~13.5V. Voltages exceeding this clamp value should not be applied to the GATE pin. The output stage provides very low impedance to overshoot and undershoot. VC - This pin is for separate collector supply to the output gate drive. Separate VC and PGND helps decouple the IC’s analog circuitry from the high power gate drive noise. (Decouple VC to PGND with a low ESR 0.1µF or larger capacitor.) VCC - VCC is the power connection for the device. Although quiescent current, ICC, is low, it is dependent on the frequency of operation. To optimize noise immunity, bypass VCC to LGND with a ceramic capacitor as close to the VCC and LGND pins as possible. The total supply current (IC plus ICC) will be higher, depending on the load applied to GATE. Total current is the sum of the quiescent current and the average gate current. Knowing the operating frequency, fsw, and the MOSFET gate charge, Qg, the average GATE output current can be calculated in Equation 5: VREF - The 5V reference voltage output. Bypass to LGND with a 0.01µF or larger capacitor to filter this output as needed. Using capacitance less than this value may result in unstable operation. tC 0.655 RT CT S (EQ. 1) tD RT – CT LN 0.001 RT 3.6 – 0.001 RT 1.9 – ------------------------------------------- S (EQ. 2) fsw 1 tD tC + ----------------- = Hz (EQ. 3) (EQ. 4) Dmax tC fsw = (EQ. 5) Igate Qg fsw = A |
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