ISL9103, ISL9103A

FN6828 Rev 3.00

Page 9 of 14

December 9, 2015

Block Diagram

Theory of Operation

The ISL9103, ISL9103A is a step-down switching regulator

optimized for battery-powered handheld applications. The

regulator operates at typical 2.4MHz fixed switching frequency

under heavy load condition to allow small external inductor and

capacitors to be used for minimal printed-circuit board (PCB)

area. At light load, the regulator can automatically enter the

skip mode (PFM mode) to reduce the switching frequency to

minimize the switching loss and to maximize the battery life.

The quiescent current under skip mode, and under no load and

no switch condition is typically only 20µA. The supply current is

typically only 0.05µA when the regulator is disabled.

PWM Control Scheme

The ISL9103, ISL9103A uses the peak-current-mode

pulse-width modulation (PWM) control scheme for fast

transient response and pulse-by-pulse current limiting. Figure

22 shows the circuit functional block diagram. The current loop

consists of the oscillator, the PWM comparator COMP, current

sensing circuit, and the slope compensation for the current

loop stability. The current sensing circuit consists of the

resistance of the P-Channel MOSFET when it is turned on and

the Current Sense Amplifier (CSA). The control reference for

the current loops comes from the Error Amplifier (EAMP) of the

voltage loop.

The PWM operation is initialized by the clock from the

oscillator. The P-Channel MOSFET is turned on at the

beginning of a PWM cycle and the current in the P-Channel

MOSFET starts ramping up. When the sum of the CSA output

and the compensation slope reaches the control reference of

the current loop, the PWM comparator COMP sends a signal

to the PWM logic to turn off the P-Channel MOSFET and to

turn on the N-Channel MOSFET. The N-MOSFET remains on till

the end of the PWM cycle. Figure 23 shows the typical operating

waveforms during the normal PWM operation. The dotted lines

illustrate the sum of the slope compensation ramp and the CSA

output.

SW

+

CS A

+

+

OC P

VR EF 1

SK IP

+

X

SL O PE

CO M P

SO

FT

STA

RT

SO F T -

S T ART

VR EF

EA M P

CO M P

PW M /PF M

L OGIC

CO NT RO L L E R

PRO T EC T IO N

DR IVER

FB

S HUT DO W N

VIN

GN D

O S CIL L AT O R

Z E RO -CRO S S

SE N S IN G

B L EED IN G

FE T

*N O T E

BA NDG AP

SC P

+

EN

S HUT DO W N

100



VR E F 2

VR EF3

*N OT E : F OR F IX E D O U T P U T OP T ION S ON L Y

FIGURE 22. FUNCTIONAL BLOCK DIAGRAM

NOTE: For Adjustable output version, the internal feedback resistor divider is disabled and the FB pin

is directly connected to the error amplifier.