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ISL29147IROMZ-T7 Datasheet(PDF) 4 Page - Renesas Technology Corp |
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ISL29147IROMZ-T7 Datasheet(HTML) 4 Page - Renesas Technology Corp |
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4 / 15 page  ISL29147 FN8409 Rev 3.00 Page 4 of 15 January 6, 2015 LED DRIVER (IRDR PIN) tr Rise Time for IRDR Sink Current RLOAD = 15Ω at IRDR pin, 20% to 80% 25 ns tf Fall time for IRDR Sink Current RLOAD = 15Ω at IRDR pin, 80% to 20% 15 ns IIRDR_0 IRDR Sink Current PROX_DR = 0; VIRDR = 0.5V 31.25 mA IIRDR_1 IRDR Sink Current PROX_DR = 1; VIRDR = 0.5V 62.5 mA IIRDR_2 IRDR Sink Current PROX_DR = 2; VIRDR = 0.5V 125 mA IIRDR_3 IRDR Sink Current PROX_DR = 3; VIRDR = 0.5V 250 mA IIRDR_LEAK IRDR Leakage Current PROX_EN = 0; VIRDR = 3.63V 0.001 1 µA VIRDR IRDR Pin Voltage Compliance Register bit PROX_DR = 0 0.50 4.3 V tPULSE IIRDR On Time Per PROX Reading 90 µs Electrical Specifications VDD = 3.0V, TA = +25°C. (Continued) PARAMETER DESCRIPTION TEST CONDITION MIN (Note 10)TYP MAX (Note 10)UNITS IR-LED Specifications TA = +25°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10)TYP MAX (Note 10)UNITS VF IR-LED Forward Voltage IF = 100mA 1.8 V VR IR-LED Reverse Voltage 5.5 V λP IR-LED Peak Output Wavelength IF = 100mA 855 nm Δλ IR-LED Spectral Half-Width IF = 100mA 30 nm ΦE IR-LED Radiant Power IF = 100mA 38 mW I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C (Note 8). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10)TYP MAX (Note 10)UNITS VI2C Supply Voltage Range for I2C Interface 1.7 3.63 V fSCL SCL Clock Frequency 400 kHz VIL SCL and SDA Input Low Voltage 0.55 V VIH SCL and SDA Input High Voltage 1.25 V Vhys Hysteresis of Schmitt Trigger Input 0.05VDD V VOL Low-level Output Voltage (open-drain) at 4mA Sink Current 0.4 V Ii Input Leakage for each SDA, SCL Pin -10 10 µA tSP Pulse Width of Spikes that must be Suppressed by the Input Filter 50 ns tAA SCL Falling Edge to SDA Output Data Valid 900 ns Ci Capacitance for each SDA and SCL Pin 10 pF tHD:STA Hold Time START Condition After this period, the first clock pulse is generated 600 ns tLOW LOW Period of the SCL Clock Measured at the 30% of VDD crossing 1300 ns tHIGH HIGH Period of the SCL Clock 600 ns tSU:STA Set-up Time for a START Condition 600 ns tHD:DAT Data Hold Time 30 ns |
Similar Part No. - ISL29147IROMZ-T7 |
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Similar Description - ISL29147IROMZ-T7 |
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