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PCA9545AD Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCA9545AD Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 27 page 9397 750 14311 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 3 March 2005 9 of 27 Philips Semiconductors PCA9545A 4-channel I2C switch with interrupt logic and reset 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). 8.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9). Fig 8. Bit transfer mba607 data line stable; data valid change of data allowed SDA SCL Fig 9. Definition of START and STOP conditions mba608 SDA SCL P STOP condition SDA SCL S START condition |
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